Changeset 7cedc46a in mainline


Ignore:
Timestamp:
2011-03-05T19:31:22Z (14 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
5dab9237, 89ae871, f16a76b
Parents:
dc790e1
Message:

cstyle

File:
1 edited

Legend:

Unmodified
Added
Removed

  • boot/arch/mips32/src/asm.S

    rdc790e1 r7cedc46a  
    5252        mtc0 $a0, $status
    5353       
    54         /* Setup CPU map (on msim this code
    55            is executed in parallel on all CPUs,
    56            but it not an issue) */
     54        /*
     55         * Setup CPU map (on msim this code
     56         * is executed in parallel on all CPUs,
     57         * but it not an issue).
     58         */
    5759        la $a0, PA2KA(CPUMAP_OFFSET)
    5860       
    … …  
    105107        lw $k1, ($k0)
    106108       
    107         /* If we are not running on BSP
    108            then end in an infinite loop  */
     109        /*
     110         * If we are not running on BSP
     111         * then end in an infinite loop.
     112         */
    109113        beq $k1, $zero, bsp
    110114        nop
    … …  
    138142
    139143jump_to_kernel:
    140         #
    141         # TODO:
    142         # Make sure that the I-cache, D-cache and memory are mutually coherent
    143         # before passing control to the copied code.
    144         #
     144        /*
     145         * TODO:
     146         *
     147         * Make sure that the I-cache, D-cache and memory are mutually
     148         * coherent before passing control to the copied code.
     149         */
    145150        j $a0
    146151        nop
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