Changeset 7bdcc45 in mainline for kernel/arch


Ignore:
Timestamp:
2010-12-16T16:38:49Z (15 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
7837101
Parents:
8e58f94 (diff), eb221e5 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

Location:
kernel/arch
Files:
86 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/abs32le/include/istate.h

    r8e58f94 r7bdcc45  
    3737
    3838#ifdef KERNEL
     39
    3940#include <typedefs.h>
    4041#include <verify.h>
    4142#include <trace.h>
    42 #else
     43
     44#else /* KERNEL */
     45
    4346#include <sys/types.h>
     47
    4448#define NO_TRACE
    4549#define REQUIRES_EXTENT_MUTABLE(arg)
    4650#define WRITES(arg)
    47 #endif
     51
     52#endif /* KERNEL */
    4853
    4954/*
    … …  
    6368           context originated from user space. */
    6469       
    65         return !(istate->ip & 0x80000000);
     70        return !(istate->ip & UINT32_C(0x80000000));
    6671}
    6772

  • kernel/arch/abs32le/include/mm/as.h

    r8e58f94 r7bdcc45  
    3838#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH  0
    3939
    40 #define KERNEL_ADDRESS_SPACE_START_ARCH  ((unsigned long) 0x80000000)
    41 #define KERNEL_ADDRESS_SPACE_END_ARCH    ((unsigned long) 0xffffffff)
    42 #define USER_ADDRESS_SPACE_START_ARCH    ((unsigned long) 0x00000000)
    43 #define USER_ADDRESS_SPACE_END_ARCH      ((unsigned long) 0x7fffffff)
     40#define KERNEL_ADDRESS_SPACE_START_ARCH  UINT32_C(0x80000000)
     41#define KERNEL_ADDRESS_SPACE_END_ARCH    UINT32_C(0xffffffff)
     42#define USER_ADDRESS_SPACE_START_ARCH    UINT32_C(0x00000000)
     43#define USER_ADDRESS_SPACE_END_ARCH      UINT32_C(0x7fffffff)
    4444
    4545#define USTACK_ADDRESS_ARCH  (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1))

  • kernel/arch/abs32le/include/mm/page.h

    r8e58f94 r7bdcc45  
    4444#ifdef KERNEL
    4545
    46 #define KA2PA(x)  (((uintptr_t) (x)) - 0x80000000)
    47 #define PA2KA(x)  (((uintptr_t) (x)) + 0x80000000)
     46#define KA2PA(x)  (((uintptr_t) (x)) - UINT32_C(0x80000000))
     47#define PA2KA(x)  (((uintptr_t) (x)) + UINT32_C(0x80000000))
    4848
    4949/*
    … …  
    6565
    6666/* Macros calculating indices for each level. */
    67 #define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ff)
     67#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ffU)
    6868#define PTL1_INDEX_ARCH(vaddr)  0
    6969#define PTL2_INDEX_ARCH(vaddr)  0
    70 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ff)
     70#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ffU)
    7171
    7272/* Get PTE address accessors for each level. */

  • kernel/arch/abs32le/include/types.h

    r8e58f94 r7bdcc45  
    4646typedef uint32_t ipl_t;
    4747
    48 typedef uint32_t unative_t;
     48typedef uint32_t sysarg_t;
    4949typedef int32_t native_t;
    5050typedef uint32_t atomic_count_t;
    … …  
    5353} fncptr_t;
    5454
    55 #define PRIp  "x"  /**< Format for uintptr_t. */
    56 #define PRIs  "u"  /**< Format for size_t. */
     55#define INTN_C(c)   INT32_C(c)
     56#define UINTN_C(c)  UINT32_C(c)
    5757
    58 #define PRId8   "d"    /**< Format for int8_t. */
    59 #define PRId16  "d"    /**< Format for int16_t. */
    60 #define PRId32  "d"    /**< Format for int32_t. */
    61 #define PRId64  "lld"  /**< Format for int64_t. */
    62 #define PRIdn   "d"    /**< Format for native_t. */
    63 
    64 #define PRIu8   "u"    /**< Format for uint8_t. */
    65 #define PRIu16  "u"    /**< Format for uint16_t. */
    66 #define PRIu32  "u"    /**< Format for uint32_t. */
    67 #define PRIu64  "llu"  /**< Format for uint64_t. */
    68 #define PRIun   "u"    /**< Format for unative_t. */
    69 
    70 #define PRIx8   "x"    /**< Format for hexadecimal (u)int8_t. */
    71 #define PRIx16  "x"    /**< Format for hexadecimal (u)int16_t. */
    72 #define PRIx32  "x"    /**< Format for hexadecimal (u)uint32_t. */
    73 #define PRIx64  "llx"  /**< Format for hexadecimal (u)int64_t. */
    74 #define PRIxn   "x"    /**< Format for hexadecimal (u)native_t. */
     58#define PRIdn  PRId32  /**< Format for native_t. */
     59#define PRIun  PRIu32  /**< Format for sysarg_t. */
     60#define PRIxn  PRIx32  /**< Format for hexadecimal sysarg_t. */
     61#define PRIua  PRIu32  /**< Format for atomic_count_t. */
    7562
    7663#endif

  • kernel/arch/abs32le/src/abs32le.c

    r8e58f94 r7bdcc45  
    8686}
    8787
    88 unative_t sys_tls_set(unative_t addr)
     88sysarg_t sys_tls_set(sysarg_t addr)
    8989{
    9090        return EOK;

  • kernel/arch/amd64/include/asm.h

    r8e58f94 r7bdcc45  
    304304}
    305305
    306 NO_TRACE static inline unative_t read_msr(uint32_t msr)
     306NO_TRACE static inline sysarg_t read_msr(uint32_t msr)
    307307{
    308308        uint32_t ax, dx;
    … …  
    343343        asm volatile (
    344344                "invlpg %[addr]\n"
    345                 :: [addr] "m" (*((unative_t *) addr))
     345                :: [addr] "m" (*((sysarg_t *) addr))
    346346        );
    347347}
    … …  
    398398}
    399399
    400 #define GEN_READ_REG(reg) NO_TRACE static inline unative_t read_ ##reg (void) \
     400#define GEN_READ_REG(reg) NO_TRACE static inline sysarg_t read_ ##reg (void) \
    401401        { \
    402                 unative_t res; \
     402                sysarg_t res; \
    403403                asm volatile ( \
    404404                        "movq %%" #reg ", %[res]" \
    … …  
    408408        }
    409409
    410 #define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (unative_t regn) \
     410#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (sysarg_t regn) \
    411411        { \
    412412                asm volatile ( \

  • kernel/arch/amd64/include/context.h

    r8e58f94 r7bdcc45  
    2727 */
    2828
    29 /** @addtogroup amd64   
     29/** @addtogroup amd64
    3030 * @{
    3131 */
    … …  
    4444 * panic sooner or later
    4545 */
    46 #define SP_DELTA     16
     46#define SP_DELTA  16
    4747
    4848#define context_set(c, _pc, stack, size) \

  • kernel/arch/amd64/include/context_offset.h

    r8e58f94 r7bdcc45  
    3030#define KERN_amd64_CONTEXT_OFFSET_H_
    3131
    32 #define OFFSET_SP  0x0
    33 #define OFFSET_PC  0x8
    34 #define OFFSET_RBX 0x10
    35 #define OFFSET_RBP 0x18
    36 #define OFFSET_R12 0x20
    37 #define OFFSET_R13 0x28
    38 #define OFFSET_R14 0x30
    39 #define OFFSET_R15 0x38
     32#define OFFSET_SP   0x00
     33#define OFFSET_PC   0x08
     34#define OFFSET_RBX  0x10
     35#define OFFSET_RBP  0x18
     36#define OFFSET_R12  0x20
     37#define OFFSET_R13  0x28
     38#define OFFSET_R14  0x30
     39#define OFFSET_R15  0x38
    4040
    4141#ifdef KERNEL
    42 # define OFFSET_IPL 0x40
     42        #define OFFSET_IPL 0x40
    4343#else
    44 # define OFFSET_TLS 0x40
     44        #define OFFSET_TLS 0x40
    4545#endif
    4646
    4747#ifdef __ASM__
    4848
    49 # ctx: address of the structure with saved context 
     49# ctx: address of the structure with saved context
    5050# pc: return address
    5151.macro CONTEXT_SAVE_ARCH_CORE ctx:req pc:req
    … …  
    6161.endm
    6262
    63 # ctx: address of the structure with saved context 
     63# ctx: address of the structure with saved context
    6464.macro CONTEXT_RESTORE_ARCH_CORE ctx:req pc:req
    6565        movq OFFSET_R15(\ctx), %r15
    … …  
    6868        movq OFFSET_R12(\ctx), %r12
    6969        movq OFFSET_RBP(\ctx), %rbp
    70         movq OFFSET_RBX(\ctx), %rbx     
     70        movq OFFSET_RBX(\ctx), %rbx
    7171       
    7272        movq OFFSET_SP(\ctx), %rsp   # ctx->sp -> %rsp

  • kernel/arch/amd64/include/cpu.h

    r8e58f94 r7bdcc45  
    3636#define KERN_amd64_CPU_H_
    3737
    38 #define RFLAGS_CF       (1 << 0)
    39 #define RFLAGS_PF       (1 << 2)
    40 #define RFLAGS_AF       (1 << 4)
    41 #define RFLAGS_ZF       (1 << 6)
    42 #define RFLAGS_SF       (1 << 7)
    43 #define RFLAGS_TF       (1 << 8)
    44 #define RFLAGS_IF       (1 << 9)
    45 #define RFLAGS_DF       (1 << 10)
    46 #define RFLAGS_OF       (1 << 11)
    47 #define RFLAGS_NT       (1 << 14)
    48 #define RFLAGS_RF       (1 << 16)
     38#define RFLAGS_CF  (1 << 0)
     39#define RFLAGS_PF  (1 << 2)
     40#define RFLAGS_AF  (1 << 4)
     41#define RFLAGS_ZF  (1 << 6)
     42#define RFLAGS_SF  (1 << 7)
     43#define RFLAGS_TF  (1 << 8)
     44#define RFLAGS_IF  (1 << 9)
     45#define RFLAGS_DF  (1 << 10)
     46#define RFLAGS_OF  (1 << 11)
     47#define RFLAGS_NT  (1 << 14)
     48#define RFLAGS_RF  (1 << 16)
    4949
    5050#define EFER_MSR_NUM    0xc0000080

  • kernel/arch/amd64/include/debugger.h

    r8e58f94 r7bdcc45  
    4141
    4242/* Flags that are passed to breakpoint_add function */
    43 #define BKPOINT_INSTR       0x1
    44 #define BKPOINT_WRITE       0x2
    45 #define BKPOINT_READ_WRITE  0x4
     43#define BKPOINT_INSTR       0x1U
     44#define BKPOINT_WRITE       0x2U
     45#define BKPOINT_READ_WRITE  0x4U
    4646
    47 #define BKPOINT_CHECK_ZERO  0x8
     47#define BKPOINT_CHECK_ZERO  0x8U
    4848
    4949

  • kernel/arch/amd64/include/istate.h

    r8e58f94 r7bdcc45  
    3737
    3838#ifdef KERNEL
     39
    3940#include <typedefs.h>
    4041#include <trace.h>
    41 #else
     42
     43#else /* KERNEL */
     44
    4245#include <sys/types.h>
     46
    4347#define NO_TRACE
    44 #endif
     48
     49#endif /* KERNEL */
    4550
    4651/** This is passed to interrupt handlers */
    … …  
    6166        uint64_t r14;
    6267        uint64_t r15;
    63         uint64_t alignment;     /* align rbp_frame on multiple of 16 */
    64         uint64_t rbp_frame;     /* imitation of frame pointer linkage */
    65         uint64_t rip_frame;     /* imitation of return address linkage */
    66         uint64_t error_word;    /* real or fake error word */
     68        uint64_t alignment;   /* align rbp_frame on multiple of 16 */
     69        uint64_t rbp_frame;   /* imitation of frame pointer linkage */
     70        uint64_t rip_frame;   /* imitation of return address linkage */
     71        uint64_t error_word;  /* real or fake error word */
    6772        uint64_t rip;
    6873        uint64_t cs;
    6974        uint64_t rflags;
    70         uint64_t rsp;           /* only if istate_t is from uspace */
    71         uint64_t ss;            /* only if istate_t is from uspace */
     75        uint64_t rsp;         /* only if istate_t is from uspace */
     76        uint64_t ss;          /* only if istate_t is from uspace */
    7277} istate_t;
    7378
    … …  
    7580NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    7681{
    77         return !(istate->rip & 0x8000000000000000);
     82        return !(istate->rip & UINT64_C(0x8000000000000000));
    7883}
    7984

  • kernel/arch/amd64/include/mm/as.h

    r8e58f94 r7bdcc45  
    3636#define KERN_amd64_AS_H_
    3737
    38 #define ADDRESS_SPACE_HOLE_START        0x0000800000000000ULL
    39 #define ADDRESS_SPACE_HOLE_END          0xffff7fffffffffffULL
     38#define ADDRESS_SPACE_HOLE_START  UINT64_C(0x0000800000000000)
     39#define ADDRESS_SPACE_HOLE_END    UINT64_C(0xffff7fffffffffff)
    4040
    4141#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH  0
    4242
    43 #define KERNEL_ADDRESS_SPACE_START_ARCH 0xffff800000000000ULL
    44 #define KERNEL_ADDRESS_SPACE_END_ARCH   0xffffffffffffffffULL
     43#define KERNEL_ADDRESS_SPACE_START_ARCH  UINT64_C(0xffff800000000000)
     44#define KERNEL_ADDRESS_SPACE_END_ARCH    UINT64_C(0xffffffffffffffff)
    4545
    46 #define USER_ADDRESS_SPACE_START_ARCH   0x0000000000000000ULL
    47 #define USER_ADDRESS_SPACE_END_ARCH     0x00007fffffffffffULL
     46#define USER_ADDRESS_SPACE_START_ARCH  UINT64_C(0x0000000000000000)
     47#define USER_ADDRESS_SPACE_END_ARCH    UINT64_C(0x00007fffffffffff)
    4848
    4949#define USTACK_ADDRESS_ARCH  (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1))

  • kernel/arch/amd64/include/mm/page.h

    r8e58f94 r7bdcc45  
    5555#ifndef __ASM__
    5656
    57 #define KA2PA(x)  (((uintptr_t) (x)) - 0xffff800000000000)
    58 #define PA2KA(x)  (((uintptr_t) (x)) + 0xffff800000000000)
     57#define KA2PA(x)  (((uintptr_t) (x)) - UINT64_C(0xffff800000000000))
     58#define PA2KA(x)  (((uintptr_t) (x)) + UINT64_C(0xffff800000000000))
    5959
    6060#else /* __ASM__ */
    … …  
    7878
    7979/* Macros calculating indices into page tables in each level. */
    80 #define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 39) & 0x1ff)
    81 #define PTL1_INDEX_ARCH(vaddr)  (((vaddr) >> 30) & 0x1ff)
    82 #define PTL2_INDEX_ARCH(vaddr)  (((vaddr) >> 21) & 0x1ff)
    83 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x1ff)
     80#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 39) & 0x1ffU)
     81#define PTL1_INDEX_ARCH(vaddr)  (((vaddr) >> 30) & 0x1ffU)
     82#define PTL2_INDEX_ARCH(vaddr)  (((vaddr) >> 21) & 0x1ffU)
     83#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x1ffU)
    8484
    8585/* Get PTE address accessors for each level. */
    … …  
    205205        pte_t *p = &pt[i];
    206206       
    207         p->addr_12_31 = (a >> 12) & 0xfffff;
     207        p->addr_12_31 = (a >> 12) & UINT32_C(0xfffff);
    208208        p->addr_32_51 = a >> 32;
    209209}

  • kernel/arch/amd64/include/pm.h

    r8e58f94 r7bdcc45  
    7575#define AR_WRITABLE   (1 << 1)
    7676#define AR_READABLE   (1 << 1)
    77 #define AR_TSS        (0x09)
    78 #define AR_INTERRUPT  (0x0e)
    79 #define AR_TRAP       (0x0f)
     77#define AR_TSS        (0x09U)
     78#define AR_INTERRUPT  (0x0eU)
     79#define AR_TRAP       (0x0fU)
    8080
    8181#define DPL_KERNEL  (PL_KERNEL << 5)

  • kernel/arch/amd64/include/proc/thread.h

    r8e58f94 r7bdcc45  
    4141
    4242typedef struct {
    43         unative_t tls;
     43        sysarg_t tls;
    4444        /** User and kernel RSP for syscalls. */
    4545        uint64_t syscall_rsp[2];

  • kernel/arch/amd64/include/types.h

    r8e58f94 r7bdcc45  
    4343typedef uint64_t ipl_t;
    4444
    45 typedef uint64_t unative_t;
     45typedef uint64_t sysarg_t;
    4646typedef int64_t native_t;
    4747typedef uint64_t atomic_count_t;
    … …  
    5050} fncptr_t;
    5151
    52 /* Formats for uintptr_t, size_t */
    53 #define PRIp  "llx"
    54 #define PRIs  "llu"
     52#define INTN_C(c)   INT64_C(c)
     53#define UINTN_C(c)  UINT64_C(c)
    5554
    56 /* Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */
    57 #define PRId8   "d"
    58 #define PRId16  "d"
    59 #define PRId32  "d"
    60 #define PRId64  "lld"
    61 #define PRIdn   "lld"
    62 
    63 #define PRIu8   "u"
    64 #define PRIu16  "u"
    65 #define PRIu32  "u"
    66 #define PRIu64  "llu"
    67 #define PRIun   "llu"
    68 
    69 #define PRIx8   "x"
    70 #define PRIx16  "x"
    71 #define PRIx32  "x"
    72 #define PRIx64  "llx"
    73 #define PRIxn   "llx"
     55#define PRIdn  PRId64  /**< Format for native_t. */
     56#define PRIun  PRIu64  /**< Format for sysarg_t. */
     57#define PRIxn  PRIx64  /**< Format for hexadecimal sysarg_t. */
     58#define PRIua  PRIu64  /**< Format for atomic_count_t. */
    7459
    7560#endif

  • kernel/arch/amd64/src/amd64.c

    r8e58f94 r7bdcc45  
    256256 * we need not to go to CPL0 to read it.
    257257 */
    258 unative_t sys_tls_set(unative_t addr)
     258sysarg_t sys_tls_set(sysarg_t addr)
    259259{
    260260        THREAD->arch.tls = addr;

  • kernel/arch/amd64/src/boot/memmap.c

    r8e58f94 r7bdcc45  
    3535#include <arch/boot/memmap.h>
    3636
    37 uint8_t e820counter = 0xff;
     37uint8_t e820counter = 0xffU;
    3838e820memmap_t e820table[MEMMAP_E820_MAX_RECORDS];
    3939

  • kernel/arch/amd64/src/cpu/cpu.c

    r8e58f94 r7bdcc45  
    4747 * Contains only non-MP-Specification specific SMP code.
    4848 */
    49 #define AMD_CPUID_EBX  0x68747541
    50 #define AMD_CPUID_ECX  0x444d4163
    51 #define AMD_CPUID_EDX  0x69746e65
     49#define AMD_CPUID_EBX  UINT32_C(0x68747541)
     50#define AMD_CPUID_ECX  UINT32_C(0x444d4163)
     51#define AMD_CPUID_EDX  UINT32_C(0x69746e65)
    5252
    53 #define INTEL_CPUID_EBX  0x756e6547
    54 #define INTEL_CPUID_ECX  0x6c65746e
    55 #define INTEL_CPUID_EDX  0x49656e69
    56 
     53#define INTEL_CPUID_EBX  UINT32_C(0x756e6547)
     54#define INTEL_CPUID_ECX  UINT32_C(0x6c65746e)
     55#define INTEL_CPUID_EDX  UINT32_C(0x49656e69)
    5756
    5857enum vendor {

  • kernel/arch/amd64/src/debugger.c

    r8e58f94 r7bdcc45  
    125125       
    126126        /* Disable breakpoint in DR7 */
    127         unative_t dr7 = read_dr7();
    128         dr7 &= ~(0x2 << (curidx * 2));
     127        sysarg_t dr7 = read_dr7();
     128        dr7 &= ~(0x02U << (curidx * 2));
    129129       
    130130        /* Setup DR register */
    … …  
    147147               
    148148                /* Set type to requested breakpoint & length*/
    149                 dr7 &= ~(0x3 << (16 + 4 * curidx));
    150                 dr7 &= ~(0x3 << (18 + 4 * curidx));
     149                dr7 &= ~(0x03U << (16 + 4 * curidx));
     150                dr7 &= ~(0x03U << (18 + 4 * curidx));
    151151               
    152152                if (!(flags & BKPOINT_INSTR)) {
    153153#ifdef __32_BITS__
    154                         dr7 |= ((unative_t) 0x3) << (18 + 4 * curidx);
     154                        dr7 |= ((sysarg_t) 0x03U) << (18 + 4 * curidx);
    155155#endif
    156156                       
    157157#ifdef __64_BITS__
    158                         dr7 |= ((unative_t) 0x2) << (18 + 4 * curidx);
     158                        dr7 |= ((sysarg_t) 0x02U) << (18 + 4 * curidx);
    159159#endif
    160160                       
    161161                        if ((flags & BKPOINT_WRITE))
    162                                 dr7 |= ((unative_t) 0x1) << (16 + 4 * curidx);
     162                                dr7 |= ((sysarg_t) 0x01U) << (16 + 4 * curidx);
    163163                        else if ((flags & BKPOINT_READ_WRITE))
    164                                 dr7 |= ((unative_t) 0x3) << (16 + 4 * curidx);
     164                                dr7 |= ((sysarg_t) 0x03U) << (16 + 4 * curidx);
    165165                }
    166166               
    167167                /* Enable global breakpoint */
    168                 dr7 |= 0x2 << (curidx * 2);
     168                dr7 |= 0x02U << (curidx * 2);
    169169               
    170170                write_dr7(dr7);
    … …  
    227227        if (!(breakpoints[slot].flags & BKPOINT_INSTR)) {
    228228                if ((breakpoints[slot].flags & BKPOINT_CHECK_ZERO)) {
    229                         if (*((unative_t *) breakpoints[slot].address) != 0)
     229                        if (*((sysarg_t *) breakpoints[slot].address) != 0)
    230230                                return;
    231231                       
    232                         printf("*** Found ZERO on address %" PRIp " (slot %d) ***\n",
    233                             breakpoints[slot].address, slot);
     232                        printf("*** Found ZERO on address %p (slot %d) ***\n",
     233                            (void *) breakpoints[slot].address, slot);
    234234                } else {
    235                         printf("Data watchpoint - new data: %" PRIp "\n",
    236                             *((unative_t *) breakpoints[slot].address));
    237                 }
    238         }
    239        
    240         printf("Reached breakpoint %d:%" PRIp " (%s)\n", slot, getip(istate),
    241             symtab_fmt_name_lookup(getip(istate)));
     235                        printf("Data watchpoint - new data: %#" PRIxn "\n",
     236                            *((sysarg_t *) breakpoints[slot].address));
     237                }
     238        }
     239       
     240        printf("Reached breakpoint %d:%p (%s)\n", slot,
     241            (void *) getip(istate), symtab_fmt_name_lookup(getip(istate)));
    242242       
    243243#ifdef CONFIG_KCONSOLE
    … …  
    260260        }
    261261       
    262         cur->address = NULL;
     262        cur->address = (uintptr_t) NULL;
    263263       
    264264        setup_dr(slot);
    … …  
    279279#endif
    280280       
    281         unative_t dr6 = read_dr6();
     281        sysarg_t dr6 = read_dr6();
    282282       
    283283        unsigned int i;
    … …  
    313313        unsigned int i;
    314314        for (i = 0; i < BKPOINTS_MAX; i++)
    315                 breakpoints[i].address = NULL;
     315                breakpoints[i].address = (uintptr_t) NULL;
    316316       
    317317#ifdef CONFIG_KCONSOLE
    … …  
    363363                       
    364364#ifdef __32_BITS__
    365                         printf("%-4u %7" PRIs " %p %s\n", i,
    366                             breakpoints[i].counter, breakpoints[i].address,
     365                        printf("%-4u %7zu %p %s\n", i,
     366                            breakpoints[i].counter, (void *) breakpoints[i].address,
    367367                            symbol);
    368368#endif
    369369                       
    370370#ifdef __64_BITS__
    371                         printf("%-4u %7" PRIs " %p %s\n", i,
    372                             breakpoints[i].counter, breakpoints[i].address,
     371                        printf("%-4u %7zu %p %s\n", i,
     372                            breakpoints[i].counter, (void *) breakpoints[i].address,
    373373                            symbol);
    374374#endif
    … …  
    384384int cmd_del_breakpoint(cmd_arg_t *argv)
    385385{
    386         unative_t bpno = argv->intval;
     386        sysarg_t bpno = argv->intval;
    387387        if (bpno > BKPOINTS_MAX) {
    388388                printf("Invalid breakpoint number.\n");
    … …  
    405405                flags = BKPOINT_WRITE;
    406406       
    407         printf("Adding breakpoint on address: %p\n", argv->intval);
    408        
    409         int id = breakpoint_add((void *)argv->intval, flags, -1);
     407        printf("Adding breakpoint on address: %p\n",
     408            (void *) argv->intval);
     409       
     410        int id = breakpoint_add((void *) argv->intval, flags, -1);
    410411        if (id < 0)
    411412                printf("Add breakpoint failed.\n");

  • kernel/arch/amd64/src/interrupt.c

    r8e58f94 r7bdcc45  
    6565void istate_decode(istate_t *istate)
    6666{
    67         printf("cs =%p\trip=%p\trfl=%p\terr=%p\n",
    68             istate->cs, istate->rip, istate->rflags, istate->error_word);
    69 
     67        printf("cs =%#0" PRIx64 "\trip=%p\t"
     68            "rfl=%#0" PRIx64 "\terr=%#0" PRIx64 "\n",
     69            istate->cs, (void *) istate->rip,
     70            istate->rflags, istate->error_word);
     71       
    7072        if (istate_from_uspace(istate))
    71                 printf("ss =%p\n", istate->ss);
    72        
    73         printf("rax=%p\trbx=%p\trcx=%p\trdx=%p\n",
     73                printf("ss =%#0" PRIx64 "\n", istate->ss);
     74       
     75        printf("rax=%#0" PRIx64 "\trbx=%#0" PRIx64 "\t"
     76            "rcx=%#0" PRIx64 "\trdx=%#0" PRIx64 "\n",
    7477            istate->rax, istate->rbx, istate->rcx, istate->rdx);
     78       
    7579        printf("rsi=%p\trdi=%p\trbp=%p\trsp=%p\n",
    76             istate->rsi, istate->rdi, istate->rbp,
    77             istate_from_uspace(istate) ? istate->rsp : (uintptr_t)&istate->rsp);
    78         printf("r8 =%p\tr9 =%p\tr10=%p\tr11=%p\n",
     80            (void *) istate->rsi, (void *) istate->rdi,
     81            (void *) istate->rbp,
     82            istate_from_uspace(istate) ? ((void *) istate->rsp) :
     83            &istate->rsp);
     84       
     85        printf("r8 =%#0" PRIx64 "\tr9 =%#0" PRIx64 "\t"
     86            "r10=%#0" PRIx64 "\tr11=%#0" PRIx64 "\n",
    7987            istate->r8, istate->r9, istate->r10, istate->r11);
    80         printf("r12=%p\tr13=%p\tr14=%p\tr15=%p\n",
     88       
     89        printf("r12=%#0" PRIx64 "\tr13=%#0" PRIx64 "\t"
     90            "r14=%#0" PRIx64 "\tr15=%#0" PRIx64 "\n",
    8191            istate->r12, istate->r13, istate->r14, istate->r15);
    8292}

  • kernel/arch/amd64/src/mm/page.c

    r8e58f94 r7bdcc45  
    8989       
    9090        if (as_page_fault(page, access, istate) == AS_PF_FAULT) {
    91                 fault_if_from_uspace(istate, "Page fault: %#x.", page);
     91                fault_if_from_uspace(istate, "Page fault: %p.", (void *) page);
    9292                panic_memtrap(istate, access, page, NULL);
    9393        }
    … …  
    9797{
    9898        if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH))
    99                 panic("Unable to map physical memory %p (%" PRIs " bytes).", physaddr,
    100                     size);
     99                panic("Unable to map physical memory %p (%zu bytes).",
     100                    (void *) physaddr, size);
    101101       
    102102        uintptr_t virtaddr = PA2KA(last_frame);

  • kernel/arch/amd64/src/pm.c

    r8e58f94 r7bdcc45  
    2828 */
    2929
    30 /** @addtogroup amd64   
     30/** @addtogroup amd64
    3131 * @{
    3232 */
    … …  
    5252        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    5353        /* KTEXT descriptor */
    54         { .limit_0_15  = 0xffff,
    55           .base_0_15   = 0, 
    56           .base_16_23  = 0, 
    57           .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, 
    58           .limit_16_19 = 0xf,
    59           .available   = 0, 
    60           .longmode    = 1, 
     54        { .limit_0_15  = 0xffffU,
     55          .base_0_15   = 0,
     56          .base_16_23  = 0,
     57          .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
     58          .limit_16_19 = 0x0fU,
     59          .available   = 0,
     60          .longmode    = 1,
    6161          .special     = 0,
    62           .granularity = 1, 
     62          .granularity = 1,
    6363          .base_24_31  = 0 },
    6464        /* KDATA descriptor */
    65         { .limit_0_15  = 0xffff,
    66           .base_0_15   = 0, 
    67           .base_16_23  = 0, 
    68           .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 
    69           .limit_16_19 = 0xf,
    70           .available   = 0, 
    71           .longmode    = 0, 
    72           .special     = 0, 
    73           .granularity = 1, 
     65        { .limit_0_15  = 0xffffU,
     66          .base_0_15   = 0,
     67          .base_16_23  = 0,
     68          .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
     69          .limit_16_19 = 0x0fU,
     70          .available   = 0,
     71          .longmode    = 0,
     72          .special     = 0,
     73          .granularity = 1,
    7474          .base_24_31  = 0 },
    7575        /* UDATA descriptor */
    76         { .limit_0_15  = 0xffff,
    77           .base_0_15   = 0, 
    78           .base_16_23  = 0, 
    79           .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 
    80           .limit_16_19 = 0xf,
    81           .available   = 0, 
    82           .longmode    = 0, 
    83           .special     = 1, 
    84           .granularity = 1, 
     76        { .limit_0_15  = 0xffffU,
     77          .base_0_15   = 0,
     78          .base_16_23  = 0,
     79          .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
     80          .limit_16_19 = 0x0fU,
     81          .available   = 0,
     82          .longmode    = 0,
     83          .special     = 1,
     84          .granularity = 1,
    8585          .base_24_31  = 0 },
    8686        /* UTEXT descriptor */
    87         { .limit_0_15  = 0xffff,
    88           .base_0_15   = 0, 
    89           .base_16_23  = 0, 
    90           .access      = AR_PRESENT | AR_CODE | DPL_USER, 
    91           .limit_16_19 = 0xf,
    92           .available   = 0, 
    93           .longmode    = 1, 
    94           .special     = 0, 
    95           .granularity = 1, 
     87        { .limit_0_15  = 0xffffU,
     88          .base_0_15   = 0,
     89          .base_16_23  = 0,
     90          .access      = AR_PRESENT | AR_CODE | DPL_USER,
     91          .limit_16_19 = 0x0fU,
     92          .available   = 0,
     93          .longmode    = 1,
     94          .special     = 0,
     95          .granularity = 1,
    9696          .base_24_31  = 0 },
    9797        /* KTEXT 32-bit protected, for protected mode before long mode */
    98         { .limit_0_15  = 0xffff,
    99           .base_0_15   = 0, 
    100           .base_16_23  = 0, 
    101           .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, 
    102           .limit_16_19 = 0xf,
    103           .available   = 0, 
    104           .longmode    = 0, 
     98        { .limit_0_15  = 0xffffU,
     99          .base_0_15   = 0,
     100          .base_16_23  = 0,
     101          .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
     102          .limit_16_19 = 0x0fU,
     103          .available   = 0,
     104          .longmode    = 0,
    105105          .special     = 1,
    106           .granularity = 1, 
     106          .granularity = 1,
    107107          .base_24_31  = 0 },
    108108        /* TSS descriptor - set up will be completed later,
    … …  
    111111        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    112112        /* VESA Init descriptor */
    113 #ifdef CONFIG_FB       
    114         { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL,
    115           0xf, 0, 0, 0, 0, 0
     113#ifdef CONFIG_FB
     114        {
     115                0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL,
     116                    0xf, 0, 0, 0, 0, 0
    116117        }
    117118#endif
    … …  
    129130{
    130131        tss_descriptor_t *td = (tss_descriptor_t *) d;
    131 
    132         td->base_0_15 = base & 0xffff;
    133         td->base_16_23 = ((base) >> 16) & 0xff;
    134         td->base_24_31 = ((base) >> 24) & 0xff;
     132       
     133        td->base_0_15 = base & 0xffffU;
     134        td->base_16_23 = ((base) >> 16) & 0xffU;
     135        td->base_24_31 = ((base) >> 24) & 0xffU;
    135136        td->base_32_63 = ((base) >> 32);
    136137}
    … …  
    140141        tss_descriptor_t *td = (tss_descriptor_t *) d;
    141142       
    142         td->limit_0_15 = limit & 0xffff;
    143         td->limit_16_19 = (limit >> 16) & 0xf;
     143        td->limit_0_15 = limit & 0xffffU;
     144        td->limit_16_19 = (limit >> 16) & 0x0fU;
    144145}
    145146
    … …  
    149150         * Offset is a linear address.
    150151         */
    151         d->offset_0_15 = offset & 0xffff;
    152         d->offset_16_31 = offset >> 16 & 0xffff;
     152        d->offset_0_15 = offset & 0xffffU;
     153        d->offset_16_31 = (offset >> 16) & 0xffffU;
    153154        d->offset_32_63 = offset >> 32;
    154155}
    … …  
    165166{
    166167        idescriptor_t *d;
    167         int i;
    168 
     168        unsigned int i;
     169       
    169170        for (i = 0; i < IDT_ITEMS; i++) {
    170171                d = &idt[i];
    171 
     172               
    172173                d->unused = 0;
    173174                d->selector = GDT_SELECTOR(KTEXT_DES);
    174 
     175               
    175176                d->present = 1;
    176                 d->type = AR_INTERRUPT; /* masking interrupt */
     177                d->type = AR_INTERRUPT;  /* masking interrupt */
    177178        }
    178 
     179       
    179180        d = &idt[0];
    180181        idt_setoffset(d++, (uintptr_t) &int_0);

  • kernel/arch/arm32/include/types.h

    r8e58f94 r7bdcc45  
    5050typedef uint32_t ipl_t;
    5151
    52 typedef uint32_t unative_t;
     52typedef uint32_t sysarg_t;
    5353typedef int32_t native_t;
    5454typedef uint32_t atomic_count_t;
    … …  
    5757} fncptr_t;
    5858
    59 #define PRIp "x"  /**< Format for uintptr_t. */
    60 #define PRIs "u"  /**< Format for size_t. */
     59#define INTN_C(c)   INT32_C(c)
     60#define UINTN_C(c)  UINT32_C(c)
    6161
    62 #define PRId8 "d"     /**< Format for int8_t. */
    63 #define PRId16 "d"    /**< Format for int16_t. */
    64 #define PRId32 "d"    /**< Format for int32_t. */
    65 #define PRId64 "lld"  /**< Format for int64_t. */
    66 #define PRIdn "d"     /**< Format for native_t. */
    67 
    68 #define PRIu8 "u"     /**< Format for uint8_t. */
    69 #define PRIu16 "u"    /**< Format for uint16_t. */
    70 #define PRIu32 "u"    /**< Format for uint32_t. */
    71 #define PRIu64 "llu"  /**< Format for uint64_t. */
    72 #define PRIun "u"     /**< Format for unative_t. */
    73 
    74 #define PRIx8 "x"     /**< Format for hexadecimal (u)int8_t. */
    75 #define PRIx16 "x"    /**< Format for hexadecimal (u)int16_t. */
    76 #define PRIx32 "x"    /**< Format for hexadecimal (u)uint32_t. */
    77 #define PRIx64 "llx"  /**< Format for hexadecimal (u)int64_t. */
    78 #define PRIxn "x"     /**< Format for hexadecimal (u)native_t. */
     62#define PRIdn  PRId32  /**< Format for native_t. */
     63#define PRIun  PRIu32  /**< Format for sysarg_t. */
     64#define PRIxn  PRIx32  /**< Format for hexadecimal sysarg_t. */
     65#define PRIua  PRIu32  /**< Format for atomic_count_t. */
    7966
    8067#endif

  • kernel/arch/arm32/src/exception.c

    r8e58f94 r7bdcc45  
    175175void istate_decode(istate_t *istate)
    176176{
    177         printf("r0 =%#0.8lx\tr1 =%#0.8lx\tr2 =%#0.8lx\tr3 =%#0.8lx\n",
     177        printf("r0 =%#0" PRIx32 "\tr1 =%#0" PRIx32 "\t"
     178            "r2 =%#0" PRIx32 "\tr3 =%#0" PRIx32 "\n",
    178179            istate->r0, istate->r1, istate->r2, istate->r3);
    179         printf("r4 =%#0.8lx\tr5 =%#0.8lx\tr6 =%#0.8lx\tr7 =%#0.8lx\n",
     180        printf("r4 =%#" PRIx32 "\tr5 =%#0" PRIx32 "\t"
     181            "r6 =%#0" PRIx32 "\tr7 =%#0" PRIx32 "\n",
    180182            istate->r4, istate->r5, istate->r6, istate->r7);
    181         printf("r8 =%#0.8lx\tr9 =%#0.8lx\tr10=%#0.8lx\tfp =%#0.8lx\n",
    182             istate->r8, istate->r9, istate->r10, istate->fp);
    183         printf("r12=%#0.8lx\tsp =%#0.8lx\tlr =%#0.8lx\tspsr=%#0.8lx\n",
    184             istate->r12, istate->sp, istate->lr, istate->spsr);
     183        printf("r8 =%#0" PRIx32 "\tr9 =%#0" PRIx32 "\t"
     184            "r10=%#0" PRIx32 "\tfp =%p\n",
     185            istate->r8, istate->r9, istate->r10,
     186            (void *) istate->fp);
     187        printf("r12=%#0" PRIx32 "\tsp =%p\tlr =%p\tspsr=%p\n",
     188            istate->r12, (void *) istate->sp,
     189            (void *) istate->lr, (void *) istate->spsr);
    185190}
    186191

  • kernel/arch/arm32/src/mach/testarm/testarm.c

    r8e58f94 r7bdcc45  
    123123        sysinfo_set_item_val("kbd", NULL, true);
    124124        sysinfo_set_item_val("kbd.inr", NULL, GXEMUL_KBD_IRQ);
    125         sysinfo_set_item_val("kbd.address.virtual", NULL, (unative_t) gxemul_kbd);
     125        sysinfo_set_item_val("kbd.address.virtual", NULL, (sysarg_t) gxemul_kbd);
    126126#endif
    127127}

  • kernel/arch/arm32/src/mm/page.c

    r8e58f94 r7bdcc45  
    9393            KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) {
    9494                panic("Unable to map physical memory %p (%d bytes).",
    95                     physaddr, size);
     95                    (void *) physaddr, size);
    9696        }
    9797       

  • kernel/arch/arm32/src/mm/page_fault.c

    r8e58f94 r7bdcc45  
    141141        if (instr.condition == 0xf) {
    142142                panic("page_fault - instruction does not access memory "
    143                     "(instr_code: %x, badvaddr:%x).", instr, badvaddr);
     143                    "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
     144                    instr_union.pc, (void *) badvaddr);
    144145                return PF_ACCESS_EXEC;
    145146        }
    … …  
    160161
    161162        panic("page_fault - instruction doesn't access memory "
    162             "(instr_code: %x, badvaddr:%x).", instr, badvaddr);
     163            "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
     164            instr_union.pc, (void *) badvaddr);
    163165
    164166        return PF_ACCESS_EXEC;

  • kernel/arch/ia32/include/asm.h

    r8e58f94 r7bdcc45  
    6464}
    6565
    66 #define GEN_READ_REG(reg) NO_TRACE static inline unative_t read_ ##reg (void) \
     66#define GEN_READ_REG(reg) NO_TRACE static inline sysarg_t read_ ##reg (void) \
    6767        { \
    68                 unative_t res; \
     68                sysarg_t res; \
    6969                asm volatile ( \
    7070                        "movl %%" #reg ", %[res]" \
    … …  
    7474        }
    7575
    76 #define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (unative_t regn) \
     76#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (sysarg_t regn) \
    7777        { \
    7878                asm volatile ( \
    … …  
    366366        asm volatile (
    367367                "invlpg %[addr]\n"
    368                 :: [addr] "m" (*(unative_t *) addr)
     368                :: [addr] "m" (*(sysarg_t *) addr)
    369369        );
    370370}

  • kernel/arch/ia32/include/boot/boot.h

    r8e58f94 r7bdcc45  
    3838#define BOOT_OFFSET      0x108000
    3939#define AP_BOOT_OFFSET   0x8000
    40 #define BOOT_STACK_SIZE  0x400
     40#define BOOT_STACK_SIZE  0x0400
    4141
    4242#define MULTIBOOT_HEADER_MAGIC  0x1BADB002

  • kernel/arch/ia32/include/boot/memmap.h

    r8e58f94 r7bdcc45  
    7070
    7171extern e820memmap_t e820table[MEMMAP_E820_MAX_RECORDS];
    72 extern uint8_t e820counter; 
     72extern uint8_t e820counter;
    7373
    7474#endif

  • kernel/arch/ia32/include/context.h

    r8e58f94 r7bdcc45  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    4040#include <typedefs.h>
    4141
    42 #define STACK_ITEM_SIZE 4
     42#define STACK_ITEM_SIZE  4
    4343
    4444/*
    … …  
    4848 * One item is put onto stack to support get_stack_base().
    4949 */
    50 #define SP_DELTA        (8 + STACK_ITEM_SIZE)
     50#define SP_DELTA  (8 + STACK_ITEM_SIZE)
    5151
    5252#define context_set(c, _pc, stack, size) \

  • kernel/arch/ia32/include/context_offset.h

    r8e58f94 r7bdcc45  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    3636#define KERN_ia32_CONTEXT_OFFSET_H_
    3737
    38 #define OFFSET_SP  0x0
    39 #define OFFSET_PC  0x4
    40 #define OFFSET_EBX 0x8
    41 #define OFFSET_ESI 0xC
    42 #define OFFSET_EDI 0x10
    43 #define OFFSET_EBP 0x14
     38#define OFFSET_SP   0x00
     39#define OFFSET_PC   0x04
     40#define OFFSET_EBX  0x08
     41#define OFFSET_ESI  0x0C
     42#define OFFSET_EDI  0x10
     43#define OFFSET_EBP  0x14
    4444
    45 #ifdef KERNEL 
    46 # define OFFSET_IPL 0x18
     45#ifdef KERNEL
     46        #define OFFSET_IPL 0x18
    4747#else
    48 # define OFFSET_TLS 0x18
     48        #define OFFSET_TLS 0x18
    4949#endif
    5050
     51#ifdef __ASM__
    5152
    52 #ifdef __ASM__
    53 
    54 # ctx: address of the structure with saved context
     53# ctx: address of the structure with saved context
    5554# pc: return address
    5655
    5756.macro CONTEXT_SAVE_ARCH_CORE ctx:req pc:req
    58         movl %esp,OFFSET_SP(\ctx)       # %esp -> ctx->sp       
     57        movl %esp,OFFSET_SP(\ctx)       # %esp -> ctx->sp
    5958        movl \pc,OFFSET_PC(\ctx)        # %eip -> ctx->pc
    60         movl %ebx,OFFSET_EBX(\ctx)      # %ebx -> ctx->ebx     
    61         movl %esi,OFFSET_ESI(\ctx)      # %esi -> ctx->esi     
    62         movl %edi,OFFSET_EDI(\ctx)      # %edi -> ctx->edi     
    63         movl %ebp,OFFSET_EBP(\ctx)      # %ebp -> ctx->ebp     
     59        movl %ebx,OFFSET_EBX(\ctx)      # %ebx -> ctx->ebx
     60        movl %esi,OFFSET_ESI(\ctx)      # %esi -> ctx->esi
     61        movl %edi,OFFSET_EDI(\ctx)      # %edi -> ctx->edi
     62        movl %ebp,OFFSET_EBP(\ctx)      # %ebp -> ctx->ebp
    6463.endm
    6564
    66 # ctx: address of the structure with saved context 
     65# ctx: address of the structure with saved context
    6766
    6867.macro CONTEXT_RESTORE_ARCH_CORE ctx:req pc:req
    … …  
    7574.endm
    7675
    77 #endif /* __ASM__ */ 
     76#endif /* __ASM__ */
    7877
    7978#endif
    … …  
    8180/** @}
    8281 */
    83 

  • kernel/arch/ia32/include/cpu.h

    r8e58f94 r7bdcc45  
    4444
    4545/* Support for SYSENTER and SYSEXIT */
    46 #define IA32_MSR_SYSENTER_CS    0x174
    47 #define IA32_MSR_SYSENTER_ESP   0x175
    48 #define IA32_MSR_SYSENTER_EIP   0x176
     46#define IA32_MSR_SYSENTER_CS   0x174U
     47#define IA32_MSR_SYSENTER_ESP  0x175U
     48#define IA32_MSR_SYSENTER_EIP  0x176U
    4949
    5050#ifndef __ASM__

  • kernel/arch/ia32/include/drivers/i8259.h

    r8e58f94 r7bdcc45  
    3939#include <arch/interrupt.h>
    4040
    41 #define PIC_PIC0PORT1  ((ioport8_t *) 0x20)
    42 #define PIC_PIC0PORT2  ((ioport8_t *) 0x21)
    43 #define PIC_PIC1PORT1  ((ioport8_t *) 0xa0)
    44 #define PIC_PIC1PORT2  ((ioport8_t *) 0xa1)
     41#define PIC_PIC0PORT1  ((ioport8_t *) 0x20U)
     42#define PIC_PIC0PORT2  ((ioport8_t *) 0x21U)
     43#define PIC_PIC1PORT1  ((ioport8_t *) 0xa0U)
     44#define PIC_PIC1PORT2  ((ioport8_t *) 0xa1U)
    4545
    4646#define PIC_NEEDICW4  (1 << 0)

  • kernel/arch/ia32/include/istate.h

    r8e58f94 r7bdcc45  
    3737
    3838#ifdef KERNEL
     39
    3940#include <typedefs.h>
    4041#include <trace.h>
    41 #else
     42
     43#else /* KERNEL */
     44
    4245#include <sys/types.h>
     46
    4347#define NO_TRACE
    44 #endif
     48
     49#endif /* KERNEL */
    4550
    4651typedef struct istate {
    … …  
    7782NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    7883{
    79         return !(istate->eip & 0x80000000);
     84        return !(istate->eip & UINT32_C(0x80000000));
    8085}
    8186

  • kernel/arch/ia32/include/mm/as.h

    r8e58f94 r7bdcc45  
    3636#define KERN_ia32_AS_H_
    3737
    38 #define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH      0
     38#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH  0
    3939
    40 #define KERNEL_ADDRESS_SPACE_START_ARCH         ((unsigned long) 0x80000000)
    41 #define KERNEL_ADDRESS_SPACE_END_ARCH           ((unsigned long) 0xffffffff)
    42 #define USER_ADDRESS_SPACE_START_ARCH           ((unsigned long) 0x00000000)
    43 #define USER_ADDRESS_SPACE_END_ARCH             ((unsigned long) 0x7fffffff)
     40#define KERNEL_ADDRESS_SPACE_START_ARCH  UINT32_C(0x80000000)
     41#define KERNEL_ADDRESS_SPACE_END_ARCH    UINT32_C(0xffffffff)
     42#define USER_ADDRESS_SPACE_START_ARCH    UINT32_C(0x00000000)
     43#define USER_ADDRESS_SPACE_END_ARCH      UINT32_C(0x7fffffff)
    4444
    45 #define USTACK_ADDRESS_ARCH     (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1))
     45#define USTACK_ADDRESS_ARCH  (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1))
    4646
    4747typedef struct {
    … …  
    5050#include <genarch/mm/as_pt.h>
    5151
    52 #define as_constructor_arch(as, flags)          (as != as)
    53 #define as_destructor_arch(as)                  (as != as)
    54 #define as_create_arch(as, flags)               (as != as)
     52#define as_constructor_arch(as, flags)  (as != as)
     53#define as_destructor_arch(as)          (as != as)
     54#define as_create_arch(as, flags)       (as != as)
    5555#define as_install_arch(as)
    5656#define as_deinstall_arch(as)

  • kernel/arch/ia32/include/mm/page.h

    r8e58f94 r7bdcc45  
    3939#include <trace.h>
    4040
    41 #define PAGE_WIDTH      FRAME_WIDTH
    42 #define PAGE_SIZE       FRAME_SIZE
     41#define PAGE_WIDTH  FRAME_WIDTH
     42#define PAGE_SIZE   FRAME_SIZE
    4343
    4444#ifdef KERNEL
    4545
    4646#ifndef __ASM__
    47 #       define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
    48 #       define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
    49 #else
    50 #       define KA2PA(x) ((x) - 0x80000000)
    51 #       define PA2KA(x) ((x) + 0x80000000)
    52 #endif
     47
     48#define KA2PA(x)  (((uintptr_t) (x)) - UINT32_C(0x80000000))
     49#define PA2KA(x)  (((uintptr_t) (x)) + UINT32_C(0x80000000))
     50
     51#else /* __ASM__ */
     52
     53#define KA2PA(x)  ((x) - 0x80000000)
     54#define PA2KA(x)  ((x) + 0x80000000)
     55
     56#endif /* __ASM__ */
    5357
    5458/*
    … …  
    5862
    5963/* Number of entries in each level. */
    60 #define PTL0_ENTRIES_ARCH       1024
    61 #define PTL1_ENTRIES_ARCH       0
    62 #define PTL2_ENTRIES_ARCH       0
    63 #define PTL3_ENTRIES_ARCH       1024
     64#define PTL0_ENTRIES_ARCH  1024
     65#define PTL1_ENTRIES_ARCH  0
     66#define PTL2_ENTRIES_ARCH  0
     67#define PTL3_ENTRIES_ARCH  1024
    6468
    6569/* Page table sizes for each level. */
    66 #define PTL0_SIZE_ARCH          ONE_FRAME
    67 #define PTL1_SIZE_ARCH          0
    68 #define PTL2_SIZE_ARCH          0
    69 #define PTL3_SIZE_ARCH          ONE_FRAME
     70#define PTL0_SIZE_ARCH  ONE_FRAME
     71#define PTL1_SIZE_ARCH  0
     72#define PTL2_SIZE_ARCH  0
     73#define PTL3_SIZE_ARCH  ONE_FRAME
    7074
    7175/* Macros calculating indices for each level. */
    72 #define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ff)
    73 #define PTL1_INDEX_ARCH(vaddr)  0
    74 #define PTL2_INDEX_ARCH(vaddr)  0
    75 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ff)
     76#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ffU)
     77#define PTL1_INDEX_ARCH(vaddr)  0
     78#define PTL2_INDEX_ARCH(vaddr)  0
     79#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ffU)
    7680
    7781/* Get PTE address accessors for each level. */
    … …  
    122126#define PTE_WRITABLE_ARCH(p) \
    123127        ((p)->writeable != 0)
    124 #define PTE_EXECUTABLE_ARCH(p)                  1
     128#define PTE_EXECUTABLE_ARCH(p)  1
    125129
    126130#ifndef __ASM__
    … …  
    144148
    145149/** When bit on this position is 1, a reserved bit was set in page directory. */
    146 #define PFERR_CODE_RSVD         (1 << 3)       
     150#define PFERR_CODE_RSVD         (1 << 3)
    147151
    148152/** Page Table Entry. */

  • kernel/arch/ia32/include/proc/thread.h

    r8e58f94 r7bdcc45  
    3939
    4040typedef struct {
    41         unative_t tls;
     41        sysarg_t tls;
    4242} thread_arch_t;
    4343

  • kernel/arch/ia32/include/smp/ap.h

    r8e58f94 r7bdcc45  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */

  • kernel/arch/ia32/include/smp/apic.h

    r8e58f94 r7bdcc45  
    4949
    5050/** Delivery modes. */
    51 #define DELMOD_FIXED    0x0
    52 #define DELMOD_LOWPRI   0x1
    53 #define DELMOD_SMI      0x2
     51#define DELMOD_FIXED    0x0U
     52#define DELMOD_LOWPRI   0x1U
     53#define DELMOD_SMI      0x2U
    5454/* 0x3 reserved */
    55 #define DELMOD_NMI      0x4
    56 #define DELMOD_INIT     0x5
    57 #define DELMOD_STARTUP  0x6
    58 #define DELMOD_EXTINT   0x7
     55#define DELMOD_NMI      0x4U
     56#define DELMOD_INIT     0x5U
     57#define DELMOD_STARTUP  0x6U
     58#define DELMOD_EXTINT   0x7U
    5959
    6060/** Destination modes. */
    61 #define DESTMOD_PHYS   0x0
    62 #define DESTMOD_LOGIC  0x1
     61#define DESTMOD_PHYS   0x0U
     62#define DESTMOD_LOGIC  0x1U
    6363
    6464/** Trigger Modes. */
    65 #define TRIGMOD_EDGE   0x0
    66 #define TRIGMOD_LEVEL  0x1
     65#define TRIGMOD_EDGE   0x0U
     66#define TRIGMOD_LEVEL  0x1U
    6767
    6868/** Levels. */
    69 #define LEVEL_DEASSERT  0x0
    70 #define LEVEL_ASSERT    0x1
     69#define LEVEL_DEASSERT  0x0U
     70#define LEVEL_ASSERT    0x1U
    7171
    7272/** Destination Shorthands. */
    73 #define SHORTHAND_NONE      0x0
    74 #define SHORTHAND_SELF      0x1
    75 #define SHORTHAND_ALL_INCL  0x2
    76 #define SHORTHAND_ALL_EXCL  0x3
     73#define SHORTHAND_NONE      0x0U
     74#define SHORTHAND_SELF      0x1U
     75#define SHORTHAND_ALL_INCL  0x2U
     76#define SHORTHAND_ALL_EXCL  0x3U
    7777
    7878/** Interrupt Input Pin Polarities. */
    79 #define POLARITY_HIGH  0x0
    80 #define POLARITY_LOW   0x1
     79#define POLARITY_HIGH  0x0U
     80#define POLARITY_LOW   0x1U
    8181
    8282/** Divide Values. (Bit 2 is always 0) */
    83 #define DIVIDE_2    0x0
    84 #define DIVIDE_4    0x1
    85 #define DIVIDE_8    0x2
    86 #define DIVIDE_16   0x3
    87 #define DIVIDE_32   0x8
    88 #define DIVIDE_64   0x9
    89 #define DIVIDE_128  0xa
    90 #define DIVIDE_1    0xb
     83#define DIVIDE_2    0x0U
     84#define DIVIDE_4    0x1U
     85#define DIVIDE_8    0x2U
     86#define DIVIDE_16   0x3U
     87#define DIVIDE_32   0x8U
     88#define DIVIDE_64   0x9U
     89#define DIVIDE_128  0xaU
     90#define DIVIDE_1    0xbU
    9191
    9292/** Timer Modes. */
    93 #define TIMER_ONESHOT   0x0
    94 #define TIMER_PERIODIC  0x1
     93#define TIMER_ONESHOT   0x0U
     94#define TIMER_PERIODIC  0x1U
    9595
    9696/** Delivery status. */
    97 #define DELIVS_IDLE     0x0
    98 #define DELIVS_PENDING  0x1
     97#define DELIVS_IDLE     0x0U
     98#define DELIVS_PENDING  0x1U
    9999
    100100/** Destination masks. */
    101 #define DEST_ALL  0xff
     101#define DEST_ALL  0xffU
    102102
    103103/** Dest format models. */
    104 #define MODEL_FLAT     0xf
    105 #define MODEL_CLUSTER  0x0
     104#define MODEL_FLAT     0xfU
     105#define MODEL_CLUSTER  0x0U
    106106
    107107/** Interrupt Command Register. */
    108 #define ICRlo  (0x300 / sizeof(uint32_t))
    109 #define ICRhi  (0x310 / sizeof(uint32_t))
     108#define ICRlo  (0x300U / sizeof(uint32_t))
     109#define ICRhi  (0x310U / sizeof(uint32_t))
    110110
    111111typedef struct {
    … …  
    135135
    136136/* End Of Interrupt. */
    137 #define EOI  (0x0b0 / sizeof(uint32_t))
     137#define EOI  (0x0b0U / sizeof(uint32_t))
    138138
    139139/** Error Status Register. */
    140 #define ESR  (0x280 / sizeof(uint32_t))
     140#define ESR  (0x280U / sizeof(uint32_t))
    141141
    142142typedef union {
    … …  
    157157
    158158/* Task Priority Register */
    159 #define TPR  (0x080 / sizeof(uint32_t))
     159#define TPR  (0x080U / sizeof(uint32_t))
    160160
    161161typedef union {
    … …  
    168168
    169169/** Spurious-Interrupt Vector Register. */
    170 #define SVR  (0x0f0 / sizeof(uint32_t))
     170#define SVR  (0x0f0U / sizeof(uint32_t))
    171171
    172172typedef union {
    … …  
    181181
    182182/** Time Divide Configuration Register. */
    183 #define TDCR  (0x3e0 / sizeof(uint32_t))
     183#define TDCR  (0x3e0U / sizeof(uint32_t))
    184184
    185185typedef union {
    … …  
    192192
    193193/* Initial Count Register for Timer */
    194 #define ICRT  (0x380 / sizeof(uint32_t))
     194#define ICRT  (0x380U / sizeof(uint32_t))
    195195
    196196/* Current Count Register for Timer */
    197 #define CCRT  (0x390 / sizeof(uint32_t))
     197#define CCRT  (0x390U / sizeof(uint32_t))
    198198
    199199/** LVT Timer register. */
    200 #define LVT_Tm  (0x320 / sizeof(uint32_t))
     200#define LVT_Tm  (0x320U / sizeof(uint32_t))
    201201
    202202typedef union {
    … …  
    214214
    215215/** LVT LINT registers. */
    216 #define LVT_LINT0  (0x350 / sizeof(uint32_t))
    217 #define LVT_LINT1  (0x360 / sizeof(uint32_t))
     216#define LVT_LINT0  (0x350U / sizeof(uint32_t))
     217#define LVT_LINT1  (0x360U / sizeof(uint32_t))
    218218
    219219typedef union {
    … …  
    233233
    234234/** LVT Error register. */
    235 #define LVT_Err  (0x370 / sizeof(uint32_t))
     235#define LVT_Err  (0x370U / sizeof(uint32_t))
    236236
    237237typedef union {
    … …  
    248248
    249249/** Local APIC ID Register. */
    250 #define L_APIC_ID  (0x020 / sizeof(uint32_t))
     250#define L_APIC_ID  (0x020U / sizeof(uint32_t))
    251251
    252252typedef union {
    … …  
    259259
    260260/** Local APIC Version Register */
    261 #define LAVR       (0x030 / sizeof(uint32_t))
    262 #define LAVR_Mask  0xff
    263 
    264 #define is_local_apic(x)    (((x) & LAVR_Mask & 0xf0) == 0x1)
    265 #define is_82489DX_apic(x)  ((((x) & LAVR_Mask & 0xf0) == 0x0))
    266 #define is_local_xapic(x)   (((x) & LAVR_Mask) == 0x14)
     261#define LAVR       (0x030U / sizeof(uint32_t))
     262#define LAVR_Mask  0xffU
     263
     264#define is_local_apic(x)    (((x) & LAVR_Mask & 0xf0U) == 0x1U)
     265#define is_82489DX_apic(x)  ((((x) & LAVR_Mask & 0xf0U) == 0x0U))
     266#define is_local_xapic(x)   (((x) & LAVR_Mask) == 0x14U)
    267267
    268268/** Logical Destination Register. */
    269 #define  LDR  (0x0d0 / sizeof(uint32_t))
     269#define  LDR  (0x0d0U / sizeof(uint32_t))
    270270
    271271typedef union {
    … …  
    278278
    279279/** Destination Format Register. */
    280 #define DFR  (0x0e0 / sizeof(uint32_t))
     280#define DFR  (0x0e0U / sizeof(uint32_t))
    281281
    282282typedef union {
    … …  
    289289
    290290/* IO APIC */
    291 #define IOREGSEL  (0x00 / sizeof(uint32_t))
    292 #define IOWIN     (0x10 / sizeof(uint32_t))
    293 
    294 #define IOAPICID   0x00
    295 #define IOAPICVER  0x01
    296 #define IOAPICARB  0x02
    297 #define IOREDTBL   0x10
     291#define IOREGSEL  (0x00U / sizeof(uint32_t))
     292#define IOWIN     (0x10U / sizeof(uint32_t))
     293
     294#define IOAPICID   0x00U
     295#define IOAPICVER  0x01U
     296#define IOAPICARB  0x02U
     297#define IOREDTBL   0x10U
    298298
    299299/** I/O Register Select Register. */

  • kernel/arch/ia32/include/types.h

    r8e58f94 r7bdcc45  
    4343typedef uint32_t ipl_t;
    4444
    45 typedef uint32_t unative_t;
     45typedef uint32_t sysarg_t;
    4646typedef int32_t native_t;
    4747typedef uint32_t atomic_count_t;
    … …  
    5050} fncptr_t;
    5151
    52 #define PRIp "x"  /**< Format for uintptr_t. */
    53 #define PRIs "u"  /**< Format for size_t. */
     52#define INTN_C(c)   INT32_C(c)
     53#define UINTN_C(c)  UINT32_C(c)
    5454
    55 #define PRId8 "d"     /**< Format for int8_t. */
    56 #define PRId16 "d"    /**< Format for int16_t. */
    57 #define PRId32 "d"    /**< Format for int32_t. */
    58 #define PRId64 "lld"  /**< Format for int64_t. */
    59 #define PRIdn "d"     /**< Format for native_t. */
    60 
    61 #define PRIu8 "u"     /**< Format for uint8_t. */
    62 #define PRIu16 "u"    /**< Format for uint16_t. */
    63 #define PRIu32 "u"    /**< Format for uint32_t. */
    64 #define PRIu64 "llu"  /**< Format for uint64_t. */
    65 #define PRIun "u"     /**< Format for unative_t. */
    66 
    67 #define PRIx8 "x"     /**< Format for hexadecimal (u)int8_t. */
    68 #define PRIx16 "x"    /**< Format for hexadecimal (u)int16_t. */
    69 #define PRIx32 "x"    /**< Format for hexadecimal (u)uint32_t. */
    70 #define PRIx64 "llx"  /**< Format for hexadecimal (u)int64_t. */
    71 #define PRIxn "x"     /**< Format for hexadecimal (u)native_t. */
     55#define PRIdn  PRId32  /**< Format for native_t. */
     56#define PRIun  PRIu32  /**< Format for sysarg_t. */
     57#define PRIxn  PRIx32  /**< Format for hexadecimal sysarg_t. */
     58#define PRIua  PRIu32  /**< Format for atomic_count_t. */
    7259
    7360#endif

  • kernel/arch/ia32/src/bios/bios.c

    r8e58f94 r7bdcc45  
    3636#include <typedefs.h>
    3737
    38 #define BIOS_EBDA_PTR  0x40e
     38#define BIOS_EBDA_PTR  0x40eU
    3939
    4040uintptr_t ebda = 0;
    … …  
    4343{
    4444        /* Copy the EBDA address out from BIOS Data Area */
    45         ebda = *((uint16_t *) BIOS_EBDA_PTR) * 0x10;
     45        ebda = *((uint16_t *) BIOS_EBDA_PTR) * 0x10U;
    4646}
    4747

  • kernel/arch/ia32/src/boot/memmap.c

    r8e58f94 r7bdcc45  
    3535#include <arch/boot/memmap.h>
    3636
    37 uint8_t e820counter = 0xff;
     37uint8_t e820counter = 0xffU;
    3838e820memmap_t e820table[MEMMAP_E820_MAX_RECORDS];
    3939

  • kernel/arch/ia32/src/cpu/cpu.c

    r8e58f94 r7bdcc45  
    4949 * Contains only non-MP-Specification specific SMP code.
    5050 */
    51 #define AMD_CPUID_EBX  0x68747541
    52 #define AMD_CPUID_ECX  0x444d4163
    53 #define AMD_CPUID_EDX  0x69746e65
     51#define AMD_CPUID_EBX  UINT32_C(0x68747541)
     52#define AMD_CPUID_ECX  UINT32_C(0x444d4163)
     53#define AMD_CPUID_EDX  UINT32_C(0x69746e65)
    5454
    55 #define INTEL_CPUID_EBX  0x756e6547
    56 #define INTEL_CPUID_ECX  0x6c65746e
    57 #define INTEL_CPUID_EDX  0x49656e69
     55#define INTEL_CPUID_EBX  UINT32_C(0x756e6547)
     56#define INTEL_CPUID_ECX  UINT32_C(0x6c65746e)
     57#define INTEL_CPUID_EDX  UINT32_C(0x49656e69)
    5858
    5959
    … …  
    140140                if ((info.cpuid_ebx == AMD_CPUID_EBX)
    141141                    && (info.cpuid_ecx == AMD_CPUID_ECX)
    142                         && (info.cpuid_edx == AMD_CPUID_EDX))
     142                    && (info.cpuid_edx == AMD_CPUID_EDX))
    143143                        CPU->arch.vendor = VendorAMD;
    144144               
    145145                /*
    146146                 * Check for Intel processor.
    147                  */             
     147                 */
    148148                if ((info.cpuid_ebx == INTEL_CPUID_EBX)
    149149                    && (info.cpuid_ecx == INTEL_CPUID_ECX)
    150                         && (info.cpuid_edx == INTEL_CPUID_EDX))
     150                    && (info.cpuid_edx == INTEL_CPUID_EDX))
    151151                        CPU->arch.vendor = VendorIntel;
    152152               
    153153                cpuid(INTEL_CPUID_STANDARD, &info);
    154                 CPU->arch.family = (info.cpuid_eax >> 8) & 0x0f;
    155                 CPU->arch.model = (info.cpuid_eax >> 4) & 0x0f;
    156                 CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0f;                                             
     154                CPU->arch.family = (info.cpuid_eax >> 8) & 0x0fU;
     155                CPU->arch.model = (info.cpuid_eax >> 4) & 0x0fU;
     156                CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0fU;
    157157        }
    158158}

  • kernel/arch/ia32/src/debug/stacktrace.c

    r8e58f94 r7bdcc45  
    3737#include <typedefs.h>
    3838
    39 #define FRAME_OFFSET_FP_PREV    0
    40 #define FRAME_OFFSET_RA         1
     39#define FRAME_OFFSET_FP_PREV  0
     40#define FRAME_OFFSET_RA       1
    4141
    4242bool kernel_stack_trace_context_validate(stack_trace_context_t *ctx)

  • kernel/arch/ia32/src/drivers/i8254.c

    r8e58f94 r7bdcc45  
    5454#include <ddi/device.h>
    5555
    56 #define CLK_PORT1  ((ioport8_t *) 0x40)
    57 #define CLK_PORT4  ((ioport8_t *) 0x43)
     56#define CLK_PORT1  ((ioport8_t *) 0x40U)
     57#define CLK_PORT4  ((ioport8_t *) 0x43U)
    5858
    5959#define CLK_CONST     1193180

  • kernel/arch/ia32/src/drivers/i8259.c

    r8e58f94 r7bdcc45  
    121121void pic_eoi(void)
    122122{
    123         pio_write_8((ioport8_t *)0x20, 0x20);
    124         pio_write_8((ioport8_t *)0xa0, 0x20);
     123        pio_write_8((ioport8_t *) 0x20, 0x20);
     124        pio_write_8((ioport8_t *) 0xa0, 0x20);
    125125}
    126126

  • kernel/arch/ia32/src/drivers/vesa.c

    r8e58f94 r7bdcc45  
    7070bool vesa_init(void)
    7171{
    72         if ((vesa_width == 0xffff) || (vesa_height == 0xffff))
     72        if ((vesa_width == 0xffffU) || (vesa_height == 0xffffU))
    7373                return false;
    7474       

  • kernel/arch/ia32/src/ia32.c

    r8e58f94 r7bdcc45  
    211211 * selector, and the descriptor->base is the correct address.
    212212 */
    213 unative_t sys_tls_set(unative_t addr)
     213sysarg_t sys_tls_set(sysarg_t addr)
    214214{
    215215        THREAD->arch.tls = addr;

  • kernel/arch/ia32/src/interrupt.c

    r8e58f94 r7bdcc45  
    6565void istate_decode(istate_t *istate)
    6666{
    67         printf("cs =%p\teip=%p\tefl=%p\terr=%p\n",
    68             istate->cs, istate->eip, istate->eflags, istate->error_word);
    69 
    70         printf("ds =%p\tes =%p\tfs =%p\tgs =%p\n",
     67        printf("cs =%#0" PRIx32 "\teip=%p\t"
     68            "efl=%#0" PRIx32 "\terr=%#0" PRIx32 "\n",
     69            istate->cs, (void *) istate->eip,
     70            istate->eflags, istate->error_word);
     71       
     72        printf("ds =%#0" PRIx32 "\tes =%#0" PRIx32 "\t"
     73            "fs =%#0" PRIx32 "\tgs =%#0" PRIx32 "\n",
    7174            istate->ds, istate->es, istate->fs, istate->gs);
     75       
    7276        if (istate_from_uspace(istate))
    73                 printf("ss =%p\n", istate->ss);
    74 
    75         printf("eax=%p\tebx=%p\tecx=%p\tedx=%p\n",
     77                printf("ss =%#0" PRIx32 "\n", istate->ss);
     78       
     79        printf("eax=%#0" PRIx32 "\tebx=%#0" PRIx32 "\t"
     80            "ecx=%#0" PRIx32 "\tedx=%#0" PRIx32 "\n",
    7681            istate->eax, istate->ebx, istate->ecx, istate->edx);
     82       
    7783        printf("esi=%p\tedi=%p\tebp=%p\tesp=%p\n",
    78             istate->esi, istate->edi, istate->ebp,
    79             istate_from_uspace(istate) ? istate->esp : (uintptr_t)&istate->esp);
     84            (void *) istate->esi, (void *) istate->edi,
     85            (void *) istate->ebp,
     86            istate_from_uspace(istate) ? ((void *) istate->esp) :
     87            &istate->esp);
    8088}
    8189
    … …  
    139147        );
    140148       
    141         fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR=%#0.8x.",
    142             (unative_t) mxcsr);
    143         panic_badtrap(istate, n, "SIMD FP exception, MXCSR=%#0.8x");
     149        fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR=%#0" PRIx32 ".",
     150            mxcsr);
     151        panic_badtrap(istate, n, "SIMD FP exception");
    144152}
    145153

  • kernel/arch/ia32/src/mm/frame.c

    r8e58f94 r7bdcc45  
    4444#include <align.h>
    4545#include <macros.h>
    46 
    4746#include <print.h>
    4847
    49 #define PHYSMEM_LIMIT32  0x07c000000ull
    50 #define PHYSMEM_LIMIT64  0x200000000ull
     48#define PHYSMEM_LIMIT32  UINT64_C(0x07c000000)
     49#define PHYSMEM_LIMIT64  UINT64_C(0x200000000)
    5150
    5251size_t hardcoded_unmapped_ktext_size = 0;

  • kernel/arch/ia32/src/mm/page.c

    r8e58f94 r7bdcc45  
    8282{
    8383        if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH))
    84                 panic("Unable to map physical memory %p (%d bytes).", physaddr, size);
     84                panic("Unable to map physical memory %p (%zu bytes).",
     85                    (void *) physaddr, size);
    8586       
    8687        uintptr_t virtaddr = PA2KA(last_frame);

  • kernel/arch/ia32/src/smp/apic.c

    r8e58f94 r7bdcc45  
    7272 *
    7373 */
    74 volatile uint32_t *l_apic = (uint32_t *) 0xfee00000;
    75 volatile uint32_t *io_apic = (uint32_t *) 0xfec00000;
     74volatile uint32_t *l_apic = (uint32_t *) UINT32_C(0xfee00000);
     75volatile uint32_t *io_apic = (uint32_t *) UINT32_C(0xfec00000);
    7676
    7777uint32_t apic_id_mask = 0;
    … …  
    184184         * Other interrupts will be forwarded to the lowest priority CPU.
    185185         */
    186         io_apic_disable_irqs(0xffff);
     186        io_apic_disable_irqs(0xffffU);
    187187       
    188188        irq_initialize(&l_apic_timer_irq);
    … …  
    477477{
    478478#ifdef LAPIC_VERBOSE
    479         printf("LVT on cpu%" PRIs ", LAPIC ID: %" PRIu8 "\n",
     479        printf("LVT on cpu%u, LAPIC ID: %" PRIu8 "\n",
    480480            CPU->id, l_apic_id());
    481481       

  • kernel/arch/ia32/src/smp/mps.c

    r8e58f94 r7bdcc45  
    5252 */
    5353
    54 #define FS_SIGNATURE  0x5f504d5f
    55 #define CT_SIGNATURE  0x504d4350
     54#define FS_SIGNATURE  UINT32_C(0x5f504d5f)
     55#define CT_SIGNATURE  UINT32_C(0x504d4350)
    5656
    5757static struct mps_fs *fs;

  • kernel/arch/ia64/include/bootinfo.h

    r8e58f94 r7bdcc45  
    6262        unsigned int memmap_items;
    6363       
    64         unative_t *sapic;
     64        sysarg_t *sapic;
    6565        unsigned long sys_freq;
    6666        unsigned long freq_scale;

  • kernel/arch/ia64/include/types.h

    r8e58f94 r7bdcc45  
    4343typedef uint64_t ipl_t;
    4444
    45 typedef uint64_t unative_t;
     45typedef uint64_t sysarg_t;
    4646typedef int64_t native_t;
    4747typedef uint64_t atomic_count_t;
    4848
    4949typedef struct {
    50         unative_t fnc;
    51         unative_t gp;
     50        sysarg_t fnc;
     51        sysarg_t gp;
    5252} __attribute__((may_alias)) fncptr_t;
    5353
    54 #define PRIp "lx"  /**< Format for uintptr_t. */
    55 #define PRIs "lu"  /**< Format for size_t. */
     54#define INTN_C(c)   INT64_C(c)
     55#define UINTN_C(c)  UINT64_C(c)
    5656
    57 #define PRId8 "d"    /**< Format for int8_t. */
    58 #define PRId16 "d"   /**< Format for int16_t. */
    59 #define PRId32 "d"   /**< Format for int32_t. */
    60 #define PRId64 "ld"  /**< Format for int64_t. */
    61 #define PRIdn "d"    /**< Format for native_t. */
    62 
    63 #define PRIu8 "u"    /**< Format for uint8_t. */
    64 #define PRIu16 "u"   /**< Format for uint16_t. */
    65 #define PRIu32 "u"   /**< Format for uint32_t. */
    66 #define PRIu64 "lu"  /**< Format for uint64_t. */
    67 #define PRIun "u"    /**< Format for unative_t. */
    68 
    69 #define PRIx8 "x"    /**< Format for hexadecimal (u)int8_t. */
    70 #define PRIx16 "x"   /**< Format for hexadecimal (u)int16_t. */
    71 #define PRIx32 "x"   /**< Format for hexadecimal (u)uint32_t. */
    72 #define PRIx64 "lx"  /**< Format for hexadecimal (u)int64_t. */
    73 #define PRIxn "x"    /**< Format for hexadecimal (u)native_t. */
     57#define PRIdn  PRId64  /**< Format for native_t. */
     58#define PRIun  PRIu64  /**< Format for sysarg_t. */
     59#define PRIxn  PRIx64  /**< Format for hexadecimal sysarg_t. */
     60#define PRIua  PRIu64  /**< Format for atomic_count_t. */
    7461
    7562#endif

  • kernel/arch/ia64/src/ia64.c

    r8e58f94 r7bdcc45  
    104104static void iosapic_init(void)
    105105{
    106         uint64_t IOSAPIC = PA2KA((unative_t)(iosapic_base)) | FW_OFFSET;
     106        uint64_t IOSAPIC = PA2KA((sysarg_t)(iosapic_base)) | FW_OFFSET;
    107107        int i;
    108108       
    … …  
    251251 * We use r13 (a.k.a. tp) for this purpose.
    252252 */
    253 unative_t sys_tls_set(unative_t addr)
     253sysarg_t sys_tls_set(sysarg_t addr)
    254254{
    255255        return 0;
    … …  
    274274void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
    275275{
    276         fptr->fnc = (unative_t) addr;
    277         fptr->gp = ((unative_t *) caller)[1];
     276        fptr->fnc = (sysarg_t) addr;
     277        fptr->gp = ((sysarg_t *) caller)[1];
    278278       
    279279        return (void *) fptr;

  • kernel/arch/ia64/src/interrupt.c

    r8e58f94 r7bdcc45  
    135135void istate_decode(istate_t *istate)
    136136{
    137         printf("ar.bsp=%p\tar.bspstore=%p\n", istate->ar_bsp,
    138             istate->ar_bspstore);
    139         printf("ar.rnat=%#018llx\tar.rsc=%#018llx\n", istate->ar_rnat,
    140             istate->ar_rsc);
    141         printf("ar.ifs=%#018llx\tar.pfs=%#018llx\n", istate->ar_ifs,
    142             istate->ar_pfs);
    143         printf("cr.isr=%#018llx\tcr.ipsr=%#018llx\t\n", istate->cr_isr.value,
    144             istate->cr_ipsr);
    145        
    146         printf("cr.iip=%#018llx, #%d\t(%s)\n", istate->cr_iip, istate->cr_isr.ei,
     137        printf("ar.bsp=%p\tar.bspstore=%p\n",
     138            (void *) istate->ar_bsp, (void *) istate->ar_bspstore);
     139        printf("ar.rnat=%#0" PRIx64 "\tar.rsc=%#0" PRIx64 "\n",
     140            istate->ar_rnat, istate->ar_rsc);
     141        printf("ar.ifs=%#0" PRIx64 "\tar.pfs=%#0" PRIx64 "\n",
     142            istate->ar_ifs, istate->ar_pfs);
     143        printf("cr.isr=%#0" PRIx64 "\tcr.ipsr=%#0" PRIx64 "\n",
     144            istate->cr_isr.value, istate->cr_ipsr.value);
     145       
     146        printf("cr.iip=%#0" PRIx64 ", #%u\t(%s)\n",
     147            istate->cr_iip, istate->cr_isr.ei,
    147148            symtab_fmt_name_lookup(istate->cr_iip));
    148         printf("cr.iipa=%#018llx\t(%s)\n", istate->cr_iipa,
     149        printf("cr.iipa=%#0" PRIx64 "\t(%s)\n", istate->cr_iipa,
    149150            symtab_fmt_name_lookup(istate->cr_iipa));
    150         printf("cr.ifa=%#018llx\t(%s)\n", istate->cr_ifa,
     151        printf("cr.ifa=%#0" PRIx64 "\t(%s)\n", istate->cr_ifa,
    151152            symtab_fmt_name_lookup(istate->cr_ifa));
    152153}

  • kernel/arch/ia64/src/mm/tlb.c

    r8e58f94 r7bdcc45  
    499499                page_table_unlock(AS, true);
    500500                if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
    501                         fault_if_from_uspace(istate, "Page fault at %p.", va);
     501                        fault_if_from_uspace(istate, "Page fault at %p.",
     502                            (void *) va);
    502503                        panic_memtrap(istate, PF_ACCESS_EXEC, va, NULL);
    503504                }
    … …  
    556557                        } else {
    557558                                fault_if_from_uspace(istate,
    558                                     "IO access fault at %p.", va);
     559                                    "IO access fault at %p.", (void *) va);
    559560                        }
    560561                }
    … …  
    620621                 */
    621622                if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
    622                         fault_if_from_uspace(istate, "Page fault at %p.", va);
     623                        fault_if_from_uspace(istate, "Page fault at %p.",
     624                            (void *) va);
    623625                        panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, NULL);
    624626                }
    … …  
    668670        } else {
    669671                if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
    670                         fault_if_from_uspace(istate, "Page fault at %p.", va);
     672                        fault_if_from_uspace(istate, "Page fault at %p.",
     673                            (void *) va);
    671674                        panic_memtrap(istate, PF_ACCESS_WRITE, va, NULL);
    672675                }
    … …  
    704707        } else {
    705708                if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
    706                         fault_if_from_uspace(istate, "Page fault at %p.", va);
     709                        fault_if_from_uspace(istate, "Page fault at %p.",
     710                            (void *) va);
    707711                        panic_memtrap(istate, PF_ACCESS_EXEC, va, NULL);
    708712                }
    … …  
    740744        } else {
    741745                if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
    742                         fault_if_from_uspace(istate, "Page fault at %p.", va);
     746                        fault_if_from_uspace(istate, "Page fault at %p.",
     747                            (void *) va);
    743748                        panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, NULL);
    744749                }
    … …  
    772777        ASSERT(!t->w);
    773778        if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
    774                 fault_if_from_uspace(istate, "Page fault at %p.", va);
     779                fault_if_from_uspace(istate, "Page fault at %p.",
     780                    (void *) va);
    775781                panic_memtrap(istate, PF_ACCESS_WRITE, va, NULL);
    776782        }
    … …  
    812818                page_table_unlock(AS, true);
    813819                if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
    814                         fault_if_from_uspace(istate, "Page fault at %p.", va);
     820                        fault_if_from_uspace(istate, "Page fault at %p.",
     821                            (void *) va);
    815822                        panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, NULL);
    816823                }

  • kernel/arch/mips32/include/debugger.h

    r8e58f94 r7bdcc45  
    5858
    5959typedef struct  {
    60         uintptr_t address;          /**< Breakpoint address */
    61         unative_t instruction;      /**< Original instruction */
    62         unative_t nextinstruction;  /**< Original instruction following break */
    63         unsigned int flags;         /**< Flags regarding breakpoint */
     60        uintptr_t address;         /**< Breakpoint address */
     61        sysarg_t instruction;      /**< Original instruction */
     62        sysarg_t nextinstruction;  /**< Original instruction following break */
     63        unsigned int flags;        /**< Flags regarding breakpoint */
    6464        size_t counter;
    6565        void (*bkfunc)(void *, istate_t *);
    … …  
    6868extern bpinfo_t breakpoints[BKPOINTS_MAX];
    6969
    70 extern bool is_jump(unative_t);
     70extern bool is_jump(sysarg_t);
    7171
    7272extern void debugger_init(void);

  • kernel/arch/mips32/include/fpu_context.h

    r8e58f94 r7bdcc45  
    3838#include <typedefs.h>
    3939
    40 #define FPU_CONTEXT_ALIGN    sizeof(unative_t)
     40#define FPU_CONTEXT_ALIGN    sizeof(sysarg_t)
    4141
    4242typedef struct {
    43         unative_t dregs[32];
    44         unative_t cregs[32];
     43        sysarg_t dregs[32];
     44        sysarg_t cregs[32];
    4545} fpu_context_t;
    4646

  • kernel/arch/mips32/include/types.h

    r8e58f94 r7bdcc45  
    4343typedef uint32_t ipl_t;
    4444
    45 typedef uint32_t unative_t;
     45typedef uint32_t sysarg_t;
    4646typedef int32_t native_t;
    4747typedef uint32_t atomic_count_t;
    … …  
    5050} fncptr_t;
    5151
    52 #define PRIp "x"  /**< Format for uintptr_t. */
    53 #define PRIs "u"  /**< Format for size_t. */
     52#define INTN_C(c)   INT32_C(c)
     53#define UINTN_C(c)  UINT32_C(c)
    5454
    55 #define PRId8 "d"     /**< Format for int8_t. */
    56 #define PRId16 "d"    /**< Format for int16_t. */
    57 #define PRId32 "ld"   /**< Format for int32_t. */
    58 #define PRId64 "lld"  /**< Format for int64_t. */
    59 #define PRIdn "d"     /**< Format for native_t. */
    60 
    61 #define PRIu8 "u"     /**< Format for uint8_t. */
    62 #define PRIu16 "u"    /**< Format for uint16_t. */
    63 #define PRIu32 "u"    /**< Format for uint32_t. */
    64 #define PRIu64 "llu"  /**< Format for uint64_t. */
    65 #define PRIun "u"     /**< Format for unative_t. */
    66 
    67 #define PRIx8 "x"     /**< Format for hexadecimal (u)int8_t. */
    68 #define PRIx16 "x"    /**< Format for hexadecimal (u)int16_t. */
    69 #define PRIx32 "x"    /**< Format for hexadecimal (u)uint32_t. */
    70 #define PRIx64 "llx"  /**< Format for hexadecimal (u)int64_t. */
    71 #define PRIxn "x"     /**< Format for hexadecimal (u)native_t. */
     55#define PRIdn  PRId32  /**< Format for native_t. */
     56#define PRIun  PRIu32  /**< Format for sysarg_t. */
     57#define PRIxn  PRIx32  /**< Format for hexadecimal sysarg_t. */
     58#define PRIua  PRIu32  /**< Format for atomic_count_t. */
    7259
    7360#endif

  • kernel/arch/mips32/src/cache.c

    r8e58f94 r7bdcc45  
    3939void cache_error(istate_t *istate)
    4040{
    41         panic("cache_error exception (epc=%p).", istate->epc);
     41        panic("cache_error exception (epc=%p).", (void *) istate->epc);
    4242}
    4343

  • kernel/arch/mips32/src/debugger.c

    r8e58f94 r7bdcc45  
    134134 *
    135135 */
    136 bool is_jump(unative_t instr)
     136bool is_jump(sysarg_t instr)
    137137{
    138138        unsigned int i;
    … …  
    166166                        return 0;
    167167                } else if ((breakpoints[i].address == (uintptr_t) argv->intval +
    168                     sizeof(unative_t)) || (breakpoints[i].address ==
    169                     (uintptr_t) argv->intval - sizeof(unative_t))) {
     168                    sizeof(sysarg_t)) || (breakpoints[i].address ==
     169                    (uintptr_t) argv->intval - sizeof(sysarg_t))) {
    170170                        printf("Adjacent breakpoints not supported, conflict "
    171171                            "with %d.\n", i);
    … …  
    191191        }
    192192       
    193         printf("Adding breakpoint on address %p\n", argv->intval);
     193        printf("Adding breakpoint on address %p\n", (void *) argv->intval);
    194194       
    195195        cur->address = (uintptr_t) argv->intval;
    196         cur->instruction = ((unative_t *) cur->address)[0];
    197         cur->nextinstruction = ((unative_t *) cur->address)[1];
     196        cur->instruction = ((sysarg_t *) cur->address)[0];
     197        cur->nextinstruction = ((sysarg_t *) cur->address)[1];
    198198        if (argv == &add_argv) {
    199199                cur->flags = 0;
    … …  
    209209       
    210210        /* Set breakpoint */
    211         *((unative_t *) cur->address) = 0x0d;
     211        *((sysarg_t *) cur->address) = 0x0d;
    212212        smc_coherence(cur->address);
    213213       
    … …  
    247247        smc_coherence(((uint32_t *) cur->address)[1]);
    248248       
    249         cur->address = NULL;
     249        cur->address = (uintptr_t) NULL;
    250250       
    251251        irq_spinlock_unlock(&bkpoint_lock, true);
    … …  
    267267                            breakpoints[i].address);
    268268                       
    269                         printf("%-4u %7" PRIs " %p %-8s %-9s %-10s %s\n", i,
    270                             breakpoints[i].counter, breakpoints[i].address,
     269                        printf("%-4u %7zu %p %-8s %-9s %-10s %s\n", i,
     270                            breakpoints[i].counter, (void *) breakpoints[i].address,
    271271                            ((breakpoints[i].flags & BKPOINT_INPROG) ? "true" :
    272272                            "false"), ((breakpoints[i].flags & BKPOINT_ONESHOT)
    … …  
    289289       
    290290        for (i = 0; i < BKPOINTS_MAX; i++)
    291                 breakpoints[i].address = NULL;
     291                breakpoints[i].address = (uintptr_t) NULL;
    292292       
    293293#ifdef CONFIG_KCONSOLE
    … …  
    341341                /* Reinst only breakpoint */
    342342                if ((breakpoints[i].flags & BKPOINT_REINST) &&
    343                     (fireaddr == breakpoints[i].address + sizeof(unative_t))) {
     343                    (fireaddr == breakpoints[i].address + sizeof(sysarg_t))) {
    344344                        cur = &breakpoints[i];
    345345                        break;
    … …  
    366366               
    367367                if (!(cur->flags & BKPOINT_FUNCCALL)) {
    368                         printf("***Breakpoint %u: %p in %s.\n", i, fireaddr,
     368                        printf("***Breakpoint %u: %p in %s.\n", i,
     369                            (void *) fireaddr,
    369370                            symtab_fmt_name_lookup(fireaddr));
    370371                }
    … …  
    381382                cur->flags |= BKPOINT_INPROG;
    382383        } else {
    383                 printf("***Breakpoint %d: %p in %s.\n", i, fireaddr,
     384                printf("***Breakpoint %d: %p in %s.\n", i,
     385                    (void *) fireaddr,
    384386                    symtab_fmt_name_lookup(fireaddr));
    385387               
    … …  
    417419                /* Remove one-shot breakpoint */
    418420                if ((cur->flags & BKPOINT_ONESHOT))
    419                         cur->address = NULL;
     421                        cur->address = (uintptr_t) NULL;
    420422               
    421423                /* Remove in-progress flag */

  • kernel/arch/mips32/src/exception.c

    r8e58f94 r7bdcc45  
    7474void istate_decode(istate_t *istate)
    7575{
    76         printf("epc=%p\tsta=%p\tlo =%p\thi =%p\n",
    77             istate->epc, istate->status, istate->lo, istate->hi);
    78         printf("a0 =%p\ta1 =%p\ta2 =%p\ta3 =%p\n",
     76        printf("epc=%p\tsta=%#010" PRIx32 "\t"
     77            "lo =%#010" PRIx32 "\thi =%#010" PRIx32 "\n",
     78            (void *) istate->epc, istate->status,
     79            istate->lo, istate->hi);
     80       
     81        printf("a0 =%#010" PRIx32 "\ta1 =%#010" PRIx32 "\t"
     82            "a2 =%#010" PRIx32 "\ta3 =%#010" PRIx32 "\n",
    7983            istate->a0, istate->a1, istate->a2, istate->a3);
    80         printf("t0 =%p\tt1 =%p\tt2 =%p\tt3 =%p\n",
     84       
     85        printf("t0 =%#010" PRIx32 "\tt1 =%#010" PRIx32 "\t"
     86            "t2 =%#010" PRIx32 "\tt3 =%#010" PRIx32 "\n",
    8187            istate->t0, istate->t1, istate->t2, istate->t3);
    82         printf("t4 =%p\tt5 =%p\tt6 =%p\tt7 =%p\n",
     88       
     89        printf("t4 =%#010" PRIx32 "\tt5 =%#010" PRIx32 "\t"
     90            "t6 =%#010" PRIx32 "\tt7 =%#010" PRIx32 "\n",
    8391            istate->t4, istate->t5, istate->t6, istate->t7);
    84         printf("t8 =%p\tt9 =%p\tv0 =%p\tv1 =%p\n",
     92       
     93        printf("t8 =%#010" PRIx32 "\tt9 =%#010" PRIx32 "\t"
     94            "v0 =%#010" PRIx32 "\tv1 =%#010" PRIx32 "\n",
    8595            istate->t8, istate->t9, istate->v0, istate->v1);
    86         printf("s0 =%p\ts1 =%p\ts2 =%p\ts3 =%p\n",
     96       
     97        printf("s0 =%#010" PRIx32 "\ts1 =%#010" PRIx32 "\t"
     98            "s2 =%#010" PRIx32 "\ts3 =%#010" PRIx32 "\n",
    8799            istate->s0, istate->s1, istate->s2, istate->s3);
    88         printf("s4 =%p\ts5 =%p\ts6 =%p\ts7 =%p\n",
     100       
     101        printf("s4 =%#010" PRIx32 "\ts5 =%#010" PRIx32 "\t"
     102            "s6 =%#010" PRIx32 "\ts7 =%#010" PRIx32 "\n",
    89103            istate->s4, istate->s5, istate->s6, istate->s7);
    90         printf("s8 =%p\tat =%p\tkt0=%p\tkt1=%p\n",
     104       
     105        printf("s8 =%#010" PRIx32 "\tat =%#010" PRIx32 "\t"
     106            "kt0=%#010" PRIx32 "\tkt1=%#010" PRIx32 "\n",
    91107            istate->s8, istate->at, istate->kt0, istate->kt1);
     108       
    92109        printf("sp =%p\tra =%p\tgp =%p\n",
    93             istate->sp, istate->ra, istate->gp);
     110            (void *) istate->sp, (void *) istate->ra,
     111            (void *) istate->gp);
    94112}
    95113

  • kernel/arch/mips32/src/mips32.c

    r8e58f94 r7bdcc45  
    233233 * possible to have it separately in the future.
    234234 */
    235 unative_t sys_tls_set(unative_t addr)
     235sysarg_t sys_tls_set(sysarg_t addr)
    236236{
    237237        return 0;

  • kernel/arch/mips32/src/mm/tlb.c

    r8e58f94 r7bdcc45  
    323323        uintptr_t va = cp0_badvaddr_read();
    324324       
    325         fault_if_from_uspace(istate, "TLB Refill Exception on %p.", va);
     325        fault_if_from_uspace(istate, "TLB Refill Exception on %p.",
     326            (void *) va);
    326327        panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, "TLB Refill Exception.");
    327328}
    … …  
    332333        uintptr_t va = cp0_badvaddr_read();
    333334       
    334         fault_if_from_uspace(istate, "TLB Invalid Exception on %p.", va);
     335        fault_if_from_uspace(istate, "TLB Invalid Exception on %p.",
     336            (void *) va);
    335337        panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, "TLB Invalid Exception.");
    336338}
    … …  
    340342        uintptr_t va = cp0_badvaddr_read();
    341343       
    342         fault_if_from_uspace(istate, "TLB Modified Exception on %p.", va);
     344        fault_if_from_uspace(istate, "TLB Modified Exception on %p.",
     345            (void *) va);
    343346        panic_memtrap(istate, PF_ACCESS_WRITE, va, "TLB Modified Exception.");
    344347}

  • kernel/arch/mips32/src/smp/dorder.c

    r8e58f94 r7bdcc45  
    3737#include <arch/smp/dorder.h>
    3838
    39 #define MSIM_DORDER_ADDRESS  0xB0000004
     39#define MSIM_DORDER_ADDRESS  0xB0000100
    4040
    4141#ifdef CONFIG_SMP

  • kernel/arch/ppc32/include/exception.h

    r8e58f94 r7bdcc45  
    9898}
    9999
    100 NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
     100NO_TRACE static inline sysarg_t istate_get_pc(istate_t *istate)
    101101{
    102102        return istate->pc;
    103103}
    104104
    105 NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
     105NO_TRACE static inline sysarg_t istate_get_fp(istate_t *istate)
    106106{
    107107        return istate->sp;

  • kernel/arch/ppc32/include/types.h

    r8e58f94 r7bdcc45  
    4343typedef uint32_t ipl_t;
    4444
    45 typedef uint32_t unative_t;
     45typedef uint32_t sysarg_t;
    4646typedef int32_t native_t;
    4747typedef uint32_t atomic_count_t;
    … …  
    5050} fncptr_t;
    5151
    52 /** Formats for uintptr_t, size_t */
    53 #define PRIp  "x"
    54 #define PRIs  "u"
     52#define INTN_C(c)   INT32_C(c)
     53#define UINTN_C(c)  UINT32_C(c)
    5554
    56 /** Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */
    57 #define PRId8   "d"
    58 #define PRId16  "d"
    59 #define PRId32  "d"
    60 #define PRId64  "lld"
    61 #define PRIdn   "d"
    62 
    63 #define PRIu8   "u"
    64 #define PRIu16  "u"
    65 #define PRIu32  "u"
    66 #define PRIu64  "llu"
    67 #define PRIun   "u"
    68 
    69 #define PRIx8   "x"
    70 #define PRIx16  "x"
    71 #define PRIx32  "x"
    72 #define PRIx64  "llx"
    73 #define PRIxn   "x"
     55#define PRIdn  PRId32  /**< Format for native_t. */
     56#define PRIun  PRIu32  /**< Format for sysarg_t. */
     57#define PRIxn  PRIx32  /**< Format for hexadecimal sysarg_t. */
     58#define PRIua  PRIu32  /**< Format for atomic_count_t. */
    7459
    7560#endif

  • kernel/arch/ppc32/src/cpu/cpu.c

    r8e58f94 r7bdcc45  
    6868        }
    6969       
    70         printf("cpu%" PRIs ": version=%" PRIu16" (%s), revision=%" PRIu16 "\n", cpu->id,
     70        printf("cpu%u: version=%" PRIu16" (%s), revision=%" PRIu16 "\n", cpu->id,
    7171            cpu->arch.version, name, cpu->arch.revision);
    7272}

  • kernel/arch/ppc32/src/interrupt.c

    r8e58f94 r7bdcc45  
    5454void istate_decode(istate_t *istate)
    5555{
    56         printf("r0 =%p\tr1 =%p\tr2 =%p\n", istate->r0, istate->sp, istate->r2);
    57         printf("r3 =%p\tr4 =%p\tr5 =%p\n", istate->r3, istate->r4, istate->r5);
    58         printf("r6 =%p\tr7 =%p\tr8 =%p\n", istate->r6, istate->r7, istate->r8);
    59         printf("r9 =%p\tr10=%p\tr11=%p\n",
     56        printf("r0 =%#0" PRIx32 "\tr1 =%p\tr2 =%#0" PRIx32 "\n",
     57            istate->r0, (void *) istate->sp, istate->r2);
     58       
     59        printf("r3 =%#0" PRIx32 "\tr4 =%#0" PRIx32 "\tr5 =%#0" PRIx32 "\n",
     60            istate->r3, istate->r4, istate->r5);
     61       
     62        printf("r6 =%#0" PRIx32 "\tr7 =%#0" PRIx32 "\tr8 =%#0" PRIx32 "\n",
     63            istate->r6, istate->r7, istate->r8);
     64       
     65        printf("r9 =%#0" PRIx32 "\tr10=%#0" PRIx32 "\tr11=%#0" PRIx32 "\n",
    6066            istate->r9, istate->r10, istate->r11);
    61         printf("r12=%p\tr13=%p\tr14=%p\n",
     67       
     68        printf("r12=%#0" PRIx32 "\tr13=%#0" PRIx32 "\tr14=%#0" PRIx32 "\n",
    6269            istate->r12, istate->r13, istate->r14);
    63         printf("r15=%p\tr16=%p\tr17=%p\n",
     70       
     71        printf("r15=%#0" PRIx32 "\tr16=%#0" PRIx32 "\tr17=%#0" PRIx32 "\n",
    6472            istate->r15, istate->r16, istate->r17);
    65         printf("r18=%p\tr19=%p\tr20=%p\n",
     73       
     74        printf("r18=%#0" PRIx32 "\tr19=%#0" PRIx32 "\tr20=%#0" PRIx32 "\n",
    6675            istate->r18, istate->r19, istate->r20);
    67         printf("r21=%p\tr22=%p\tr23=%p\n",
     76       
     77        printf("r21=%#0" PRIx32 "\tr22=%#0" PRIx32 "\tr23=%#0" PRIx32 "\n",
    6878            istate->r21, istate->r22, istate->r23);
    69         printf("r24=%p\tr25=%p\tr26=%p\n",
     79       
     80        printf("r24=%#0" PRIx32 "\tr25=%#0" PRIx32 "\tr26=%#0" PRIx32 "\n",
    7081            istate->r24, istate->r25, istate->r26);
    71         printf("r27=%p\tr28=%p\tr29=%p\n",
     82       
     83        printf("r27=%#0" PRIx32 "\tr28=%#0" PRIx32 "\tr29=%#0" PRIx32 "\n",
    7284            istate->r27, istate->r28, istate->r29);
    73         printf("r30=%p\tr31=%p\n", istate->r30, istate->r31);
    74         printf("cr =%p\tpc =%p\tlr =%p\n", istate->cr, istate->pc, istate->lr);
    75         printf("ctr=%p\txer=%p\tdar=%p\n",
     85       
     86        printf("r30=%#0" PRIx32 "\tr31=%#0" PRIx32 "\n",
     87            istate->r30, istate->r31);
     88       
     89        printf("cr =%#0" PRIx32 "\tpc =%p\tlr =%p\n",
     90            istate->cr, (void *) istate->pc, (void *) istate->lr);
     91       
     92        printf("ctr=%#0" PRIx32 "\txer=%#0" PRIx32 "\tdar=%#0" PRIx32 "\n",
    7693            istate->ctr, istate->xer, istate->dar);
    77         printf("srr1=%p\n", istate->srr1);
     94       
     95        printf("srr1=%p\n", (void *) istate->srr1);
    7896}
    7997
    … …  
    111129                         */
    112130#ifdef CONFIG_DEBUG
    113                         printf("cpu%" PRIs ": spurious interrupt (inum=%" PRIu8 ")\n",
     131                        printf("cpu%u: spurious interrupt (inum=%" PRIu8 ")\n",
    114132                            CPU->id, inum);
    115133#endif

  • kernel/arch/ppc32/src/mm/frame.c

    r8e58f94 r7bdcc45  
    4949        size_t i;
    5050        for (i = 0; i < memmap.cnt; i++) {
    51                 printf("%#10x %#10x\n", memmap.zones[i].start,
     51                printf("%p %#0zx\n", memmap.zones[i].start,
    5252                    memmap.zones[i].size);
    5353        }

  • kernel/arch/ppc32/src/mm/page.c

    r8e58f94 r7bdcc45  
    4949        if (last_frame + ALIGN_UP(size, PAGE_SIZE) >
    5050            KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH))
    51                 panic("Unable to map physical memory %p (%" PRIs " bytes).",
    52                     physaddr, size);
     51                panic("Unable to map physical memory %p (%zu bytes).",
     52                    (void *) physaddr, size);
    5353       
    5454        uintptr_t virtaddr = PA2KA(last_frame);

  • kernel/arch/ppc32/src/mm/tlb.c

    r8e58f94 r7bdcc45  
    111111static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
    112112{
    113         fault_if_from_uspace(istate, "PHT Refill Exception on %p.", badvaddr);
     113        fault_if_from_uspace(istate, "PHT Refill Exception on %p.",
     114            (void *) badvaddr);
    114115        panic_memtrap(istate, PF_ACCESS_UNKNOWN, badvaddr,
    115116            "PHT Refill Exception.");
    … …  
    459460                length = 0; \
    460461        \
    461         printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \
    462             sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \
    463             lower & 0xffff0000, length, mask, \
     462        printf(name ": page=%#0" PRIx32 " frame=%#0" PRIx32 \
     463            " length=%#0" PRIx32 " KB (mask=%#0" PRIx32 ")%s%s\n", \
     464            upper & UINT32_C(0xffff0000), lower & UINT32_C(0xffff0000), \
     465            length, mask, \
    464466            ((upper >> 1) & 1) ? " supervisor" : "", \
    465467            (upper & 1) ? " user" : "");
    466468
    467 
    468469void tlb_print(void)
    469470{
    … …  
    473474                uint32_t vsid = sr_get(sr << 28);
    474475               
    475                 printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr,
    476                     sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,
     476                printf("sr[%02" PRIu32 "]: vsid=%#0" PRIx32 " (asid=%" PRIu32 ")"
     477                    "%s%s\n", sr, vsid & UINT32_C(0x00ffffff),
     478                    (vsid & UINT32_C(0x00ffffff)) >> 4,
    477479                    ((vsid >> 30) & 1) ? " supervisor" : "",
    478480                    ((vsid >> 29) & 1) ? " user" : "");

  • kernel/arch/sparc64/include/mm/sun4u/tlb.h

    r8e58f94 r7bdcc45  
    678678}
    679679
    680 extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
     680extern void fast_instruction_access_mmu_miss(sysarg_t, istate_t *);
    681681extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
    682682extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);

  • kernel/arch/sparc64/include/mm/sun4v/tlb.h

    r8e58f94 r7bdcc45  
    141141}
    142142
    143 extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
    144 extern void fast_data_access_mmu_miss(unative_t, istate_t *);
    145 extern void fast_data_access_protection(unative_t, istate_t *);
     143extern void fast_instruction_access_mmu_miss(sysarg_t, istate_t *);
     144extern void fast_data_access_mmu_miss(sysarg_t, istate_t *);
     145extern void fast_data_access_protection(sysarg_t, istate_t *);
    146146
    147147extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);

  • kernel/arch/sparc64/include/types.h

    r8e58f94 r7bdcc45  
    4343typedef uint64_t ipl_t;
    4444
    45 typedef uint64_t unative_t;
     45typedef uint64_t sysarg_t;
    4646typedef int64_t native_t;
    4747typedef uint64_t atomic_count_t;
    … …  
    5252typedef uint8_t asi_t;
    5353
    54 /** Formats for uintptr_t, size_t */
    55 #define PRIp  "llx"
    56 #define PRIs  "llu"
     54#define INTN_C(c)   INT64_C(c)
     55#define UINTN_C(c)  UINT64_C(c)
    5756
    58 /** Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */
    59 #define PRId8   "d"
    60 #define PRId16  "d"
    61 #define PRId32  "d"
    62 #define PRId64  "lld"
    63 #define PRIdn   "lld"
    64 
    65 #define PRIu8   "u"
    66 #define PRIu16  "u"
    67 #define PRIu32  "u"
    68 #define PRIu64  "llu"
    69 #define PRIun   "llu"
    70 
    71 #define PRIx8   "x"
    72 #define PRIx16  "x"
    73 #define PRIx32  "x"
    74 #define PRIx64  "llx"
    75 #define PRIxn   "llx"
     57#define PRIdn  PRId64  /**< Format for native_t. */
     58#define PRIun  PRIu64  /**< Format for sysarg_t. */
     59#define PRIxn  PRIx64  /**< Format for hexadecimal sysarg_t. */
     60#define PRIua  PRIu64  /**< Format for atomic_count_t. */
    7661
    7762#endif

  • kernel/arch/sparc64/src/console.c

    r8e58f94 r7bdcc45  
    7070        ofw_tree_node_t *screen = ofw_tree_lookup(prop_scr->value);
    7171        if (!screen)
    72                 panic("Cannot find %s.", prop_scr->value);
     72                panic("Cannot find %s.", (char *) prop_scr->value);
    7373       
    7474        scr_init(screen);
    … …  
    8383        ofw_tree_node_t *keyboard = ofw_tree_lookup(prop_kbd->value);
    8484        if (!keyboard)
    85                 panic("Cannot find %s.", prop_kbd->value);
     85                panic("Cannot find %s.", (char *) prop_kbd->value);
    8686       
    8787        kbd_init(keyboard);

  • kernel/arch/sparc64/src/drivers/pci.c

    r8e58f94 r7bdcc45  
    211211                 * Unsupported model.
    212212                 */
    213                 printf("Unsupported PCI controller model (%s).\n", prop->value);
     213                printf("Unsupported PCI controller model (%s).\n",
     214                    (char *) prop->value);
    214215        }
    215216

  • kernel/arch/sparc64/src/mm/sun4u/frame.c

    r8e58f94 r7bdcc45  
    4141#include <macros.h>
    4242
    43 uintptr_t last_frame = NULL;
     43uintptr_t last_frame = (uintptr_t) NULL;
    4444
    4545/** Create memory zones according to information stored in memmap.

  • kernel/arch/sparc64/src/mm/sun4u/tlb.c

    r8e58f94 r7bdcc45  
    200200
    201201/** ITLB miss handler. */
    202 void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate)
     202void fast_instruction_access_mmu_miss(sysarg_t unused, istate_t *istate)
    203203{
    204204        uintptr_t page_16k = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
    … …  
    360360static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d)
    361361{
    362         printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
    363             "ie=%d, soft2=%#x, pfn=%#x, soft=%#x, l=%d, "
    364             "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
     362        printf("%u: vpn=%#" PRIx64 ", context=%u, v=%u, size=%u, nfo=%u, "
     363            "ie=%u, soft2=%#x, pfn=%#x, soft=%#x, l=%u, "
     364            "cp=%u, cv=%u, e=%u, p=%u, w=%u, g=%u\n", i, (uint64_t) t.vpn,
    365365            t.context, d.v, d.size, d.nfo, d.ie, d.soft2,
    366366            d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    … …  
    441441    uintptr_t va, const char *str)
    442442{
    443         fault_if_from_uspace(istate, "%s, Address=%p.", str, va);
     443        fault_if_from_uspace(istate, "%s, address=%p.", str, (void *) va);
    444444        panic_memtrap(istate, PF_ACCESS_EXEC, va, str);
    445445}
    … …  
    451451
    452452        va = tag.vpn << MMU_PAGE_WIDTH;
    453         fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va,
    454             tag.context);
     453        fault_if_from_uspace(istate, "%s, page=%p (asid=%u).", str,
     454            (void *) va, tag.context);
    455455        panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, str);
    456456}
    … …  
    462462
    463463        va = tag.vpn << MMU_PAGE_WIDTH;
    464         fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va,
    465             tag.context);
     464        fault_if_from_uspace(istate, "%s, page=%p (asid=%u).", str,
     465            (void *) va, tag.context);
    466466        panic_memtrap(istate, PF_ACCESS_WRITE, va, str);
    467467}
    … …  
    484484            sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
    485485#endif
    486            
    487         printf("DTLB SFAR: address=%p\n", sfar);
     486       
     487        printf("DTLB SFAR: address=%p\n", (void *) sfar);
    488488       
    489489        dtlb_sfsr_write(0);
    … …  
    508508#endif
    509509           
    510         printf("DTLB SFAR: address=%p\n", sfar);
     510        printf("DTLB SFAR: address=%p\n", (void *) sfar);
    511511       
    512512        dtlb_sfsr_write(0);

  • kernel/arch/sparc64/src/mm/sun4v/tlb.c

    r8e58f94 r7bdcc45  
    213213
    214214/** ITLB miss handler. */
    215 void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate)
     215void fast_instruction_access_mmu_miss(sysarg_t unused, istate_t *istate)
    216216{
    217217        uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
    … …  
    358358    const char *str)
    359359{
    360         fault_if_from_uspace(istate, "%s, Address=%p.", str, va);
     360        fault_if_from_uspace(istate, "%s, address=%p.", str,
     361            (void *) va);
    361362        panic_memtrap(istate, PF_ACCESS_EXEC, va, str);
    362363}
    … …  
    365366    uint64_t page_and_ctx, const char *str)
    366367{
    367         fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str,
    368             DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx));
     368        fault_if_from_uspace(istate, "%s, page=%p (asid=%" PRId64 ").", str,
     369            (void *) DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx));
    369370        panic_memtrap(istate, PF_ACCESS_UNKNOWN, DMISS_ADDRESS(page_and_ctx),
    370371            str);
    … …  
    374375    uint64_t page_and_ctx, const char *str)
    375376{
    376         fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str,
    377             DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx));
     377        fault_if_from_uspace(istate, "%s, page=%p (asid=%" PRId64 ").", str,
     378            (void *) DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx));
    378379        panic_memtrap(istate, PF_ACCESS_WRITE, DMISS_ADDRESS(page_and_ctx),
    379380            str);
    … …  
    399400        uint64_t errno =  __hypercall_fast3(MMU_DEMAP_ALL, 0, 0,
    400401                MMU_FLAG_DTLB | MMU_FLAG_ITLB);
    401         if (errno != HV_EOK) {
    402                 panic("Error code = %d.\n", errno);
    403         }
     402        if (errno != HV_EOK)
     403                panic("Error code = %" PRIu64 ".\n", errno);
    404404}
    405405

  • kernel/arch/sparc64/src/sun4v/md.c

    r8e58f94 r7bdcc45  
    310310        retval = retval;
    311311        if (retval != HV_EOK) {
    312                 printf("Could not retrieve machine description, error = %d.\n",
    313                     retval);
     312                printf("Could not retrieve machine description, "
     313                    "error=%" PRIu64 ".\n", retval);
    314314        }
    315315}

  • kernel/arch/sparc64/src/trap/sun4v/interrupt.c

    r8e58f94 r7bdcc45  
    8787                KA2PA(cpu_mondo_queues[CPU->id]),
    8888                CPU_MONDO_NENTRIES) != HV_EOK)
    89                         panic("Initializing mondo queue failed on CPU %d.\n",
     89                        panic("Initializing mondo queue failed on CPU %" PRIu64 ".\n",
    9090                            CPU->arch.id);
    9191}
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