Changeset 77c2b02 in mainline for uspace/drv/nic/e1k/e1k.h


Ignore:
Timestamp:
2012-01-05T15:48:08Z (13 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
9f0fb84
Parents:
c520034
Message:

e1k: add better extension points

File:
1 edited

Legend:

Unmodified
Added
Removed
  • uspace/drv/nic/e1k/e1k.h

    rc520034 r77c2b02  
    8282} e1000_tx_descriptor_t;
    8383
     84/** E1000 boards */
     85typedef enum {
     86        E1000_82541,
     87        E1000_82541REV2,
     88        E1000_82547,
     89        E1000_82572,
     90        E1000_80003ES2
     91} e1000_board_t;
     92
     93typedef struct {
     94        uint32_t eerd_start;
     95        uint32_t eerd_done;
     96       
     97        uint32_t eerd_address_offset;
     98        uint32_t eerd_data_offset;
     99} e1000_info_t;
     100
    84101/** VLAN tag bits */
    85 enum e1000_vlantag {
     102typedef enum {
    86103        VLANTAG_CFI = (1 << 12),  /**< Canonical Form Indicator */
    87 };
     104} e1000_vlantag_t;
    88105
    89106/** Transmit descriptor COMMAND field bits */
    90 enum e1000_txdescriptor_command {
     107typedef enum {
    91108        TXDESCRIPTOR_COMMAND_VLE = (1 << 6),   /**< VLAN Packet Enable */
    92109        TXDESCRIPTOR_COMMAND_RS = (1 << 3),    /**< Report Status */
    93110        TXDESCRIPTOR_COMMAND_IFCS = (1 << 1),  /**< Insert FCS */
    94111        TXDESCRIPTOR_COMMAND_EOP = (1 << 0)    /**< End Of Packet */
    95 };
     112} e1000_txdescriptor_command_t;
    96113
    97114/** Transmit descriptor STATUS field bits */
    98 enum e1000_txdescriptor_status {
     115typedef enum {
    99116        TXDESCRIPTOR_STATUS_DD = (1 << 0)  /**< Descriptor Done */
    100 };
     117} e1000_txdescriptor_status_t;
    101118
    102119/** E1000 Registers */
    103 enum e1000_registers {
     120typedef enum {
    104121        E1000_CTRL = 0x0,      /**< Device Control Register */
    105122        E1000_STATUS = 0x8,    /**< Device Status Register */
     
    130147        E1000_IMS = 0xD0,      /**< Interrupt Mask Set/Read Register */
    131148        E1000_IMC = 0xD8       /**< Interrupt Mask Clear Register */
    132 };
    133 
    134 /** EEPROM Read Register fields */
    135 enum e1000_eerd {
    136         /** Start Read */
    137         EERD_START = (1 << 0),
    138         /** Read Done */
    139         EERD_DONE = (1 << 4),
    140         /** Read Done for 82541xx and 82547GI/EI */
    141         EERD_DONE_82541XX_82547GI_EI = (1 << 1),
    142         /** Read Address offset */
    143         EERD_ADDRESS_OFFSET = 8,
    144         /** Read Address offset for 82541xx and 82547GI/EI */
    145         EERD_ADDRESS_OFFSET_82541XX_82547GI_EI = 2,
    146         /** Read Data */
    147         EERD_DATA_OFFSET = 16
    148 };
     149} e1000_registers_t;
    149150
    150151/** Device Control Register fields */
    151 enum e1000_ctrl {
     152typedef enum {
    152153        CTRL_FD = (1 << 0),    /**< Full-Duplex */
    153154        CTRL_LRST = (1 << 3),  /**< Link Reset */
     
    176177        CTRL_VME = (1 << 30),      /**< VLAN Mode Enable */
    177178        CTRL_PHY_RST = (1 << 31)   /**< PHY Reset */
    178 };
     179} e1000_ctrl_t;
    179180
    180181/** Device Status Register fields */
    181 enum e1000_status {
     182typedef enum {
    182183        STATUS_FD = (1 << 0),  /**< Link Full Duplex configuration Indication */
    183184        STATUS_LU = (1 << 1),  /**< Link Up Indication */
     
    197198        /** Link speed setting 1000 Mb/s value variant B */
    198199        STATUS_SPEED_1000B = 3,
    199 };
     200} e1000_status_t;
    200201
    201202/** Transmit IPG Register fields
     
    204205 *
    205206 */
    206 enum e1000_tipg {
     207typedef enum {
    207208        TIPG_IPGT_SHIFT = 0,    /**< IPG Transmit Time shift */
    208209        TIPG_IPGR1_SHIFT = 10,  /**< IPG Receive Time 1 */
    209210        TIPG_IPGR2_SHIFT = 20   /**< IPG Receive Time 2 */
    210 };
     211} e1000_tipg_t;
    211212
    212213/** Transmit Control Register fields */
    213 enum e1000_tctl {
     214typedef enum {
    214215        TCTL_EN = (1 << 1),    /**< Transmit Enable */
    215216        TCTL_PSP =  (1 << 3),  /**< Pad Short Packets */
    216217        TCTL_CT_SHIFT = 4,     /**< Collision Threshold shift */
    217218        TCTL_COLD_SHIFT = 12   /**< Collision Distance shift */
    218 };
     219} e1000_tctl_t;
    219220
    220221/** ICR register fields */
    221 enum e1000_icr {
     222typedef enum {
    222223        ICR_TXDW = (1 << 0),  /**< Transmit Descriptor Written Back */
    223224        ICR_RXT0 = (1 << 7)   /**< Receiver Timer Interrupt */
    224 };
     225} e1000_icr_t;
    225226
    226227/** RAH register fields */
    227 enum e1000_rah {
     228typedef enum {
    228229        RAH_AV = (1 << 31)   /**< Address Valid */
    229 };
     230} e1000_rah_t;
    230231
    231232/** RCTL register fields */
    232 enum e1000_rctl {
     233typedef enum {
    233234        RCTL_EN = (1 << 1),    /**< Receiver Enable */
    234235        RCTL_SBP = (1 << 2),   /**< Store Bad Packets */
     
    237238        RCTL_BAM = (1 << 15),  /**< Broadcast Accept Mode */
    238239        RCTL_VFE = (1 << 18)   /**< VLAN Filter Enable */
    239 };
     240} e1000_rctl_t;
    240241
    241242#endif
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