Changeset 5fcd537 in mainline

Timestamp:

2013-01-19T02:25:08Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

bad1f53

Parents:

ae86f89 (diff), 660e8fa (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes.

Includes bbxm fpu fix and other arm changes.
Merge fix: arch defines in fpu_context.c

Location:

kernel/arch/arm32

Files:

• Makefile.inc (modified) (2 diffs)
• include/barrier.h (modified) (2 diffs)
• include/cp15.h (added)
• include/regutils.h (modified) (1 diff)
• include/security_ext.h (added)
• src/fpu.s (added)
• src/fpu_context.c (modified) (10 diffs)

kernel/arch/arm32/Makefile.inc

@@ -35 +35 @@
 GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR_ARCH)) -mno-unaligned-access
 
+ifeq ($(MACHINE),beagleboardxm)
+GCC_CFLAGS += -mcpu=cortex-a8
+endif
+
 ifeq ($(CONFIG_FPU),y)
 # This is necessary to allow vmsr insn and fpexc manipulation
 # Use vfp32 to allow context save/restore of d16-d31 regs.
-GCC_CFLAGS += -mfloat-abi=hard -mfpu=vfp3
+AFLAGS += -mfloat-abi=hard -mfpu=vfp3
 endif
 
@@ -70 +74 @@
 ifeq ($(CONFIG_FPU),y)
         ARCH_SOURCES += arch/$(KARCH)/src/fpu_context.c
+        ARCH_SOURCES += arch/$(KARCH)/src/fpu.s
 endif
 

kernel/arch/arm32/include/barrier.h

@@ -39 +39 @@
 /*
  * TODO: implement true ARM memory barriers for macros below.
+ * ARMv6 introduced user access of the following commands:
+ * • Prefetch flush
+ * • Data synchronization barrier
+ * • Data memory barrier
+ * • Clean and prefetch range operations.
+ * ARM Architecture Reference Manual version I ch. B.3.2.1 p. B3-4
  */
 #define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
@@ -88 +94 @@
  */
 
-/* Available on both all supported arms,
+#ifdef PROCESSOR_ARCH_armv7_a
+#define smc_coherence(a) asm volatile ( "isb" ::: "memory")
+#define smc_coherence_block(a, l) smc_coherence(a)
+#else
+/* Available on all supported arms,
  * invalidates entire ICache so the written value does not matter. */
+//TODO might be PL1 only on armv5 -
 #define smc_coherence(a) asm volatile ( "mcr p15, 0, r0, c7, c5, 0")
 #define smc_coherence_block(a, l) smc_coherence(a)
+#endif
 
 

kernel/arch/arm32/include/regutils.h

@@ -66 +66 @@
 
 /* ARM Processor Operation Modes */
-#define USER_MODE        0x10
-#define FIQ_MODE         0x11
-#define IRQ_MODE         0x12
-#define SUPERVISOR_MODE  0x13
-#define ABORT_MODE       0x17
-#define UNDEFINED_MODE   0x1b
-#define SYSTEM_MODE      0x1f
-
+enum {
+        USER_MODE = 0x10,
+        FIQ_MODE = 0x11,
+        IRQ_MODE = 0x12,
+        SUPERVISOR_MODE = 0x13,
+        MONITOR_MODE = 0x16,
+        ABORT_MODE = 0x17,
+        HYPERVISOR_MODE = 0x1a,
+        UNDEFINED_MODE = 0x1b,
+        SYSTEM_MODE = 0x1f,
+        MODE_MASK = 0x1f,
+};
 /* [CS]PRS manipulation macros */
 #define GEN_STATUS_READ(nm, reg) \

kernel/arch/arm32/src/fpu_context.c

@@ -37 +37 @@
 #include <arch.h>
 #include <arch/types.h>
+#include <arch/security_ext.h>
+#include <arch/cp15.h>
 #include <cpu.h>
 
@@ -55 +57 @@
 };
 
+extern uint32_t fpsid_read(void);
+extern uint32_t mvfr0_read(void);
+
 enum {
         FPEXC_EX_FLAG = (1 << 31),
         FPEXC_ENABLED_FLAG = (1 << 30),
 };
+extern uint32_t fpexc_read(void);
+extern void fpexc_write(uint32_t);
 
 /** ARM Architecture Reference Manual ch. B4.1.58, p. B$-1551 */
@@ -94 +101 @@
         FPSCR_EN_ALL = FPSCR_DENORMAL_EN_FLAG | FPSCR_INEXACT_EN_FLAG | FPSCR_UNDERFLOW_EN_FLAG | FPSCR_OVERFLOW_EN_FLAG | FPSCR_ZERO_DIV_EN_FLAG | FPSCR_INVALID_OP_EN_FLAG,
 };
-
-static inline uint32_t fpscr_read()
-{
-        uint32_t reg;
-        asm volatile (
-                "vmrs %0, fpscr\n"
-                :"=r" (reg)::
-        );
-        return reg;
-}
-
-static inline void fpscr_write(uint32_t val)
-{
-        asm volatile (
-                "vmsr fpscr, %0\n"
-                ::"r" (val):
-        );
-}
-
-static inline uint32_t fpexc_read()
-{
-        uint32_t reg;
-        asm volatile (
-                "vmrs %0, fpexc\n"
-                :"=r" (reg)::
-        );
-        return reg;
-}
-
-static inline void fpexc_write(uint32_t val)
-{
-        asm volatile (
-                "vmsr fpexc, %0\n"
-                ::"r" (val):
-        );
-}
+extern uint32_t fpscr_read(void);
+extern void fpscr_write(uint32_t);
+
+extern void fpu_context_save_s32(fpu_context_t *);
+extern void fpu_context_restore_s32(fpu_context_t *);
+extern void fpu_context_save_d16(fpu_context_t *);
+extern void fpu_context_restore_d16(fpu_context_t *);
+extern void fpu_context_save_d32(fpu_context_t *);
+extern void fpu_context_restore_d32(fpu_context_t *);
 
 static void (*save_context)(fpu_context_t *ctx);
 static void (*restore_context)(fpu_context_t *ctx);
 
-/** Saves 32 single precision fpu registers.
- * @param ctx FPU context area.
- * Used by VFPv1
- */
-static void fpu_context_save_s32(fpu_context_t *ctx)
-{
-        asm volatile (
-                "vmrs r1, fpexc\n"
-                "vmrs r2, fpscr\n"
-                "stmia %0!, {r1, r2}\n"
-                "vstmia %0!, {s0-s31}\n"
-                ::"r" (ctx): "r1","r2","memory"
-        );
-}
-
-/** Restores 32 single precision fpu registers.
- * @param ctx FPU context area.
- * Used by VFPv1
- */
-static void fpu_context_restore_s32(fpu_context_t *ctx)
-{
-        asm volatile (
-                "ldmia %0!, {r1, r2}\n"
-                "vmsr fpexc, r1\n"
-                "vmsr fpscr, r2\n"
-                "vldmia %0!, {s0-s31}\n"
-                ::"r" (ctx): "r1","r2"
-        );
-}
-
-/** Saves 16 double precision fpu registers.
- * @param ctx FPU context area.
- * Used by VFPv2, VFPv3-d16, and VFPv4-d16.
- */
-static void fpu_context_save_d16(fpu_context_t *ctx)
-{
-        asm volatile (
-                "vmrs r1, fpexc\n"
-                "vmrs r2, fpscr\n"
-                "stmia %0!, {r1, r2}\n"
-                "vstmia %0!, {d0-d15}\n"
-                ::"r" (ctx): "r1","r2","memory"
-        );
-}
-
-/** Restores 16 double precision fpu registers.
- * @param ctx FPU context area.
- * Used by VFPv2, VFPv3-d16, and VFPv4-d16.
- */
-static void fpu_context_restore_d16(fpu_context_t *ctx)
-{
-        asm volatile (
-                "ldmia %0!, {r1, r2}\n"
-                "vmsr fpexc, r1\n"
-                "vmsr fpscr, r2\n"
-                "vldmia %0!, {d0-d15}\n"
-                ::"r" (ctx): "r1","r2"
-        );
-}
-
-/** Saves 32 double precision fpu registers.
- * @param ctx FPU context area.
- * Used by VFPv3-d32, VFPv4-d32, and advanced SIMD.
- */
-static void fpu_context_save_d32(fpu_context_t *ctx)
-{
-        asm volatile (
-                "vmrs r1, fpexc\n"
-                "stmia %0!, {r1}\n"
-                "vmrs r1, fpscr\n"
-                "stmia %0!, {r1}\n"
-                "vstmia %0!, {d0-d15}\n"
-                "vstmia %0!, {d16-d31}\n"
-                ::"r" (ctx): "r1","memory"
-        );
-}
-
-/** Restores 32 double precision fpu registers.
- * @param ctx FPU context area.
- * Used by VFPv3-d32, VFPv4-d32, and advanced SIMD.
- */
-static void fpu_context_restore_d32(fpu_context_t *ctx)
-{
-        asm volatile (
-                "ldmia %0!, {r1}\n"
-                "vmsr fpexc, r1\n"
-                "ldmia %0!, {r1}\n"
-                "vmsr fpscr, r1\n"
-                "vldmia %0!, {d0-d15}\n"
-                "vldmia %0!, {d16-d31}\n"
-                ::"r" (ctx): "r1"
-        );
-}
+static int fpu_have_coprocessor_access()
+{
+/* The register containing the information (CPACR) is not available on armv6-
+ * rely on user decision to use CONFIG_FPU.
+ */
+#ifdef PROCESSOR_ARC_armv7_a
+        const uint32_t cpacr = CPACR_read();
+        /* FPU needs access to coprocessor 10 and 11.
+         * Moreover they need to have same access enabledd */
+        if (((cpacr & CPACR_CP_MASK(10)) != CPACR_CP_FULL_ACCESS(10)) &&
+           ((cpacr & CPACR_CP_MASK(11)) != CPACR_CP_FULL_ACCESS(11))) {
+                printf("No access to CP10 and CP11: %" PRIx32 "\n", cpacr);
+                return 0;
+        }
+#endif
+        return 1;
+}
+
+/** Enable coprocessor access. Turn both non-secure mode bit and generic access.
+ * Cortex A8 Manual says:
+ * "You must execute an Instruction Memory Barrier (IMB) sequence immediately
+ * after an update of the Coprocessor Access Control Register, see Memory
+ * Barriers in the ARM Architecture Reference Manual. You must not attempt to
+ * execute any instructions that are affected by the change of access rights
+ * between the IMB sequence and the register update."
+ * Cortex a8 TRM ch. 3.2.27. c1, Coprocessor Access Control Register
+ *
+ * @note do we need to call secure monitor here?
+ */
+static void fpu_enable_coprocessor_access()
+{
+/* The register containing the information (CPACR) is not available on armv6-
+ * rely on user decision to use CONFIG_FPU.
+ */
+#ifndef PROCESSOR_ARCH_armv7_a
+        return;
+#endif
+
+        /* Allow coprocessor access */
+        uint32_t cpacr = CPACR_read();
+        /* FPU needs access to coprocessor 10 and 11.
+         * Moreover, they need to have same access enabled */
+        cpacr &= ~(CPACR_CP_MASK(10) | CPACR_CP_MASK(11));
+        cpacr |= (CPACR_CP_FULL_ACCESS(10) | CPACR_CP_FULL_ACCESS(11));
+        CPACR_write(cpacr);
+
+        smc_coherence(0);
+}
+
 
 void fpu_init(void)
 {
+        /* Check if we have access */
+        if (!fpu_have_coprocessor_access())
+                return;
+
         /* Clear all fpu flags */
         fpexc_write(0);
@@ -241 +181 @@
 void fpu_setup(void)
 {
-        uint32_t fpsid = 0;
-        asm volatile (
-                "vmrs %0, fpsid\n"
-                :"=r"(fpsid)::
-        );
+        /* Enable coprocessor access*/
+        fpu_enable_coprocessor_access();
+
+        /* Check if we succeeded */
+        if (!fpu_have_coprocessor_access())
+                return;
+
+        const uint32_t fpsid = fpsid_read();
         if (fpsid & FPSID_SW_ONLY_FLAG) {
                 printf("No FPU avaiable\n");
@@ -265 +208 @@
         case FPU_VFPv3_NO_COMMON:
         case FPU_VFPv3_COMMONv3: {
-                uint32_t mvfr0 = 0;
-                asm volatile (
-                        "vmrs %0,mvfr0\n"
-                        :"=r"(mvfr0)::
-                );
+                const uint32_t mvfr0 = mvfr0_read();
                 /* See page B4-1637 */
                 if ((mvfr0 & 0xf) == 0x1) {
@@ -288 +227 @@
 bool handle_if_fpu_exception(void)
 {
+        /* Check if we have access */
+        if (!fpu_have_coprocessor_access())
+                return false;
+
         const uint32_t fpexc = fpexc_read();
         if (fpexc & FPEXC_ENABLED_FLAG) {
@@ -305 +248 @@
 void fpu_enable(void)
 {
+        /* Check if we have access */
+        if (!fpu_have_coprocessor_access())
+                return;
         /* Enable FPU instructions */
         fpexc_write(fpexc_read() | FPEXC_ENABLED_FLAG);
@@ -311 +257 @@
 void fpu_disable(void)
 {
+        /* Check if we have access */
+        if (!fpu_have_coprocessor_access())
+                return;
         /* Disable FPU instructions */
         fpexc_write(fpexc_read() & ~FPEXC_ENABLED_FLAG);
@@ -317 +266 @@
 void fpu_context_save(fpu_context_t *ctx)
 {
+        /* This is only necessary if we enable fpu exceptions. */
+#if 0
         const uint32_t fpexc = fpexc_read();
 
@@ -323 +274 @@
                 //TODO implement common subarch context saving
         }
+#endif
         if (save_context)
                 save_context(ctx);