Changeset 57da95c in mainline for kernel/arch/sparc64/include/mm/tsb.h

Timestamp:

2006-09-18T11:47:28Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

29b2bbf

Parents:

f1d1f5d3

Message:

• Create a dedicated slab cache for as_t objects and switch from malloc/free to slab_alloc/slab_free for

them.

• Slightly fix and improve both the kernel and userspace atomic_add() on sparc64.

• More TSB work on the sparc64 front.

File:

• kernel/arch/sparc64/include/mm/tsb.h (modified) (3 diffs)

kernel/arch/sparc64/include/mm/tsb.h

@@ -37 +37 @@
 
 #include <arch/mm/tte.h>
+#include <arch/mm/mmu.h>
 #include <arch/types.h>
 #include <typedefs.h>
@@ -47 +48 @@
  * in TLBs - only one TLB entry will do.
  */
-#define ITSB_ENTRY_COUNT                2048
-#define DTSB_ENTRY_COUNT                2048
+#define TSB_SIZE                        2                       /* when changing this, change as.c as well */
+#define ITSB_ENTRY_COUNT                (512*(1<<TSB_SIZE))
+#define DTSB_ENTRY_COUNT                (512*(1<<TSB_SIZE))
 
 struct tsb_entry {
@@ -54 +56 @@
         tte_data_t data;
 } __attribute__ ((packed));
+typedef struct tsb_entry tsb_entry_t;
 
-typedef struct tsb_entry tsb_entry_t;
+/** TSB Base register. */
+union tsb_base_reg {
+        uint64_t value;
+        struct {
+                uint64_t base : 51;     /**< TSB base address, bits 63:13. */
+                unsigned split : 1;     /**< Split vs. common TSB for 8K and 64K pages.
+                                          *  HelenOS uses only 8K pages for user mappings,
+                                          *  so we always set this to 0.
+                                          */
+                unsigned : 9;
+                unsigned size : 3;      /**< TSB size. Number of entries is 512*2^size. */
+        } __attribute__ ((packed));
+};
+typedef union tsb_base_reg tsb_base_reg_t;
+
+/** Read ITSB Base register.
+ *
+ * @return Content of the ITSB Base register.
+ */
+static inline uint64_t itsb_base_read(void)
+{
+        return asi_u64_read(ASI_IMMU, VA_IMMU_TSB_BASE);
+}
+
+/** Read DTSB Base register.
+ *
+ * @return Content of the DTSB Base register.
+ */
+static inline uint64_t dtsb_base_read(void)
+{
+        return asi_u64_read(ASI_DMMU, VA_DMMU_TSB_BASE);
+}
+
+/** Write ITSB Base register.
+ *
+ * @param v New content of the ITSB Base register.
+ */
+static inline void itsb_base_write(uint64_t v)
+{
+        asi_u64_write(ASI_IMMU, VA_IMMU_TSB_BASE, v);
+}
+
+/** Write DTSB Base register.
+ *
+ * @param v New content of the DTSB Base register.
+ */
+static inline void dtsb_base_write(uint64_t v)
+{
+        asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v);
+}
 
 extern void tsb_invalidate(as_t *as, uintptr_t page, count_t pages);