Changeset 481c520 in mainline for arch/ia32/src/drivers/i8042.c
- Timestamp:
- 2006-02-27T12:30:11Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 02f441c0
- Parents:
- 4a2b52f
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/ia32/src/drivers/i8042.c
r4a2b52f r481c520 46 46 */ 47 47 48 #define i8042_DATA 0x6049 #define i8042_STATUS 0x6448 #define i8042_DATA 0x60 49 #define i8042_STATUS 0x64 50 50 #define i8042_BUFFER_FULL_MASK 0x01 51 52 51 53 52 /** Keyboard commands. */ … … 57 56 58 57 /* 59 60 Write 8042 Command Byte: next data byte written to port 60h is 60 placed in 8042 command register.Format: 61 62 |7|6|5|4|3|2|1|0|8042 Command Byte 63 | | | | | | | `---- 1=enable output register full interrupt 64 | | | | | | `----- should be 0 65 | | | | | `------ 1=set status register system, 0=clear 66 | | | | `------- 1=override keyboard inhibit, 0=allow inhibit 67 | | | `-------- disable keyboard I/O by driving clock line low 68 | | `--------- disable auxiliary device, drives clock line low 69 | `---------- IBM scancode translation 0=AT, 1=PC/XT 70 `----------- reserved, should be 0 71 */ 72 73 #define i8042_SET_COMMAND 0x60 74 #define i8042_COMMAND 0x49 75 #define i8042_WAIT_MASK 0x02 76 58 * 60 Write 8042 Command Byte: next data byte written to port 60h is 59 * placed in 8042 command register.Format: 60 * 61 * |7|6|5|4|3|2|1|0|8042 Command Byte 62 * | | | | | | | `---- 1=enable output register full interrupt 63 * | | | | | | `----- should be 0 64 * | | | | | `------ 1=set status register system, 0=clear 65 * | | | | `------- 1=override keyboard inhibit, 0=allow inhibit 66 * | | | `-------- disable keyboard I/O by driving clock line low 67 * | | `--------- disable auxiliary device, drives clock line low 68 * | `---------- IBM scancode translation 0=AT, 1=PC/XT 69 * `----------- reserved, should be 0 70 */ 71 72 #define i8042_SET_COMMAND 0x60 73 #define i8042_COMMAND 0x49 74 #define i8042_WAIT_MASK 0x02 77 75 78 76 #define SPECIAL '?' … … 88 86 89 87 #define ACTIVE_READ_BUFF_SIZE 16 /*Must be power of 2*/ 90 91 88 92 89 __u8 active_read_buff[ACTIVE_READ_BUFF_SIZE]={0}; … … 272 269 { 273 270 exc_register(VECTOR_KBD, "i8042_interrupt", i8042_interrupt); 274 while (inb(i8042_STATUS)&i8042_WAIT_MASK); /*Wait*/ 271 while (inb(i8042_STATUS)&i8042_WAIT_MASK) { 272 /* wait */ 273 } 275 274 outb(i8042_STATUS,i8042_SET_COMMAND); 276 while (inb(i8042_STATUS)&i8042_WAIT_MASK); /*Wait*/ 275 while (inb(i8042_STATUS)&i8042_WAIT_MASK) { 276 /* wait */ 277 } 277 278 outb(i8042_DATA,i8042_COMMAND); 278 279 … … 406 407 } 407 408 408 409 409 static __u8 active_read_buff_read(void) 410 410 { … … 428 428 429 429 430 static void active_read ed_key_pressed(__u8 sc)430 static void active_read_key_pressed(__u8 sc) 431 431 { 432 432 char *map = sc_primary_map; … … 497 497 } 498 498 499 500 499 static char key_read(chardev_t *d) 501 500 { 502 501 char ch; 503 504 502 505 503 while(!(ch=active_read_buff_read())) … … 511 509 key_released(x ^ KEY_RELEASE); 512 510 else 513 active_read ed_key_pressed(x);511 active_read_key_pressed(x); 514 512 } 515 513 return ch; 516 514 } 517 518
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