Changeset 46c20c8 in mainline for kernel/arch/sparc64/src/sun4u/start.S

Timestamp:

2010-11-26T20:08:10Z (15 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

45df59a

Parents:

fb150d78 (diff), ffdd2b9 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes.

File:

• kernel/arch/sparc64/src/sun4u/start.S (moved) (moved from kernel/arch/sparc64/src/start.S ) (7 diffs)

kernel/arch/sparc64/src/sun4u/start.S

@@ -36 +36 @@
 #include <arch/mm/tlb.h>
 #include <arch/mm/tte.h>
+#include <arch/mm/cache_spec.h>
 
 #ifdef CONFIG_SMP
@@ -60 +61 @@
 /*
  * Here is where the kernel is passed control from the boot loader.
- * 
+ *
  * The registers are expected to be in this state:
- * - %o0 starting address of physical memory + bootstrap processor flag
- *      bits 63...1:    physical memory starting address / 2
- *      bit 0:          non-zero on BSP processor, zero on AP processors
- * - %o1 bootinfo structure address (BSP only)
- * - %o2 bootinfo structure size (BSP only)
+ *  - %o0 starting address of physical memory
+ *        + bootstrap processor flag
+ *          bits 63...1: physical memory starting address / 2
+ *          bit 0:       non-zero on BSP processor, zero on AP processors
+ *  - %o1 bootinfo structure address (BSP only)
+ *
  *
  * Moreover, we depend on boot having established the following environment:
- * - TLBs are on
- * - identity mapping for the kernel image
+ *  - TLBs are on
+ *  - identity mapping for the kernel image
+ *
  */
 
@@ -267 +270 @@
         or %l3, %l5, %l3
         stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)]
-
-        /*
-         * Flush D-Cache.
-         */
-        call dcache_flush
-        nop
-
+        
+        ! flush the whole D-cache
+        set (DCACHE_SIZE - DCACHE_LINE_SIZE), %g1
+        stxa %g0, [%g1] ASI_DCACHE_TAG
+        
+0:
+        membar #Sync
+        subcc %g1, DCACHE_LINE_SIZE, %g1
+        bnz,pt %xcc, 0b
+        stxa %g0, [%g1] ASI_DCACHE_TAG
+        membar #Sync
+        
         /*
          * So far, we have not touched the stack.
@@ -281 +289 @@
         or %sp, %lo(temporary_boot_stack), %sp
         sub %sp, STACK_BIAS, %sp
-
-        sethi %hi(bootinfo), %o0
-        call memcpy                             ! copy bootinfo
-        or %o0, %lo(bootinfo), %o0
-
+        
+        /*
+         * Call arch_pre_main(bootinfo)
+         */
         call arch_pre_main
-        nop
-        
+        mov %o1, %o0
+        
+        /*
+         * Create the first stack frame.
+         */
+        save %sp, -(STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp
+        flushw
+        add %g0, -STACK_BIAS, %fp
+
         call main_bsp
         nop
@@ -295 +309 @@
 
 0:
-        ba %xcc, 0b
-        nop
+        ba,a %xcc, 0b
 
 
@@ -346 +359 @@
         ldx [%g1], %o6
 
+        /*
+         * Create the first stack frame.
+         */
+        save %sp, -(STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp
+        flushw
+        add %g0, -STACK_BIAS, %fp
+
         call main_ap
         nop
@@ -353 +373 @@
         
 0:
-        ba %xcc, 0b
-        nop
+        ba,a %xcc, 0b