Changeset 46c20c8 in mainline for kernel/arch/mips32/include


Ignore:
Timestamp:
2010-11-26T20:08:10Z (15 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
45df59a
Parents:
fb150d78 (diff), ffdd2b9 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

Location:
kernel/arch/mips32/include
Files:
1 added
23 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/mips32/include/arch.h

    rfb150d78 r46c20c8  
    3636#define KERN_mips32_ARCH_H_
    3737
    38 #define TASKMAP_MAX_RECORDS  32
    39 #define CPUMAP_MAX_RECORDS   32
     38#include <typedefs.h>
    4039
    41 #define BOOTINFO_TASK_NAME_BUFLEN 32
    42 
    43 #include <typedefs.h>
     40#define TASKMAP_MAX_RECORDS        32
     41#define CPUMAP_MAX_RECORDS         32
     42#define BOOTINFO_TASK_NAME_BUFLEN  32
    4443
    4544extern size_t cpu_count;
    4645
    4746typedef struct {
    48         uintptr_t addr;
    49         uint32_t size;
     47        void *addr;
     48        size_t size;
    5049        char name[BOOTINFO_TASK_NAME_BUFLEN];
    5150} utask_t;
    … …  
    5352typedef struct {
    5453        uint32_t cpumap;
    55         uint32_t cnt;
     54        size_t cnt;
    5655        utask_t tasks[TASKMAP_MAX_RECORDS];
    5756} bootinfo_t;

  • kernel/arch/mips32/include/asm.h

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup mips32 
     29/** @addtogroup mips32
    3030 * @{
    3131 */
    … …  
    3636#define KERN_mips32_ASM_H_
    3737
    38 #include <arch/types.h>
    3938#include <typedefs.h>
    4039#include <config.h>
     40#include <trace.h>
    4141
    42 
    43 static inline void cpu_sleep(void)
     42NO_TRACE static inline void cpu_sleep(void)
    4443{
    45         /* Most of the simulators do not support */
    46 /*      asm volatile ("wait"); */
     44        /*
     45         * Unfortunatelly most of the simulators do not support
     46         *
     47         * asm volatile (
     48         *     "wait"
     49         * );
     50         *
     51         */
    4752}
    4853
    4954/** Return base address of current stack
    50  * 
     55 *
    5156 * Return the base address of the current stack.
    5257 * The stack is assumed to be STACK_SIZE bytes long.
    5358 * The stack must start on page boundary.
     59 *
    5460 */
    55 static inline uintptr_t get_stack_base(void)
     61NO_TRACE static inline uintptr_t get_stack_base(void)
    5662{
    57         uintptr_t v;
     63        uintptr_t base;
    5864       
    5965        asm volatile (
    60                 "and %0, $29, %1\n"
    61                 : "=r" (v)
    62                 : "r" (~(STACK_SIZE-1))
     66                "and %[base], $29, %[mask]\n"
     67                : [base] "=r" (base)
     68                : [mask] "r" (~(STACK_SIZE - 1))
    6369        );
    6470       
    65         return v;
     71        return base;
    6672}
    6773
    68 extern void cpu_halt(void) __attribute__((noreturn));
    69 extern void asm_delay_loop(uint32_t t);
    70 extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg,
    71     uintptr_t entry);
    72 
    73 extern ipl_t interrupts_disable(void);
    74 extern ipl_t interrupts_enable(void);
    75 extern void interrupts_restore(ipl_t ipl);
    76 extern ipl_t interrupts_read(void);
    77 extern void asm_delay_loop(uint32_t t);
    78 
    79 static inline void pio_write_8(ioport8_t *port, uint8_t v)
     74NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
    8075{
    81         *port = v;     
     76        *port = v;
    8277}
    8378
    84 static inline void pio_write_16(ioport16_t *port, uint16_t v)
     79NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
    8580{
    86         *port = v;     
     81        *port = v;
    8782}
    8883
    89 static inline void pio_write_32(ioport32_t *port, uint32_t v)
     84NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
    9085{
    91         *port = v;     
     86        *port = v;
    9287}
    9388
    94 static inline uint8_t pio_read_8(ioport8_t *port)
     89NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
    9590{
    9691        return *port;
    9792}
    9893
    99 static inline uint16_t pio_read_16(ioport16_t *port)
     94NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
    10095{
    10196        return *port;
    10297}
    10398
    104 static inline uint32_t pio_read_32(ioport32_t *port)
     99NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
    105100{
    106101        return *port;
    107102}
     103
     104extern void cpu_halt(void) __attribute__((noreturn));
     105extern void asm_delay_loop(uint32_t);
     106extern void userspace_asm(uintptr_t, uintptr_t, uintptr_t);
     107
     108extern ipl_t interrupts_disable(void);
     109extern ipl_t interrupts_enable(void);
     110extern void interrupts_restore(ipl_t);
     111extern ipl_t interrupts_read(void);
     112extern bool interrupts_disabled(void);
    108113
    109114#endif

  • kernel/arch/mips32/include/asm/boot.h

    rfb150d78 r46c20c8  
    3636#define KERN_mips32_BOOT_H_
    3737
    38 
    3938/* Temporary stack size for boot process */
    40 #define TEMP_STACK_SIZE 0x100
     39#define TEMP_STACK_SIZE  0x100
    4140
    4241#endif

  • kernel/arch/mips32/include/asm/regname.h

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup mips32 
     29/** @addtogroup mips32
    3030 * @{
    3131 */
    … …  
    6969#define ra      31
    7070
    71 #define rindex          0
    72 #define rrandom         1
    73 #define entrylo0        2
    74 #define entrylo1        3
    75 #define context         4
    76 #define pagemask        5
    77 #define wired           6
    78 #define badvaddr        8
    79 #define count           9
    80 #define entryhi         10
    81 #define compare         11
    82 #define status          12
    83 #define cause           13
    84 #define epc             14
    85 #define rconfig         16
    86 #define lladdr          17
    87 #define watchlo         18
    88 #define watchhi         19
    89 #define xcontext        20
    90 #define rdebug          23
    91 #define depc            24
    92 #define eepc            30
     71#define rindex    0
     72#define rrandom   1
     73#define entrylo0  2
     74#define entrylo1  3
     75#define context   4
     76#define pagemask  5
     77#define wired     6
     78#define badvaddr  8
     79#define count     9
     80#define entryhi   10
     81#define compare   11
     82#define status    12
     83#define cause     13
     84#define epc       14
     85#define rconfig   16
     86#define lladdr    17
     87#define watchlo   18
     88#define watchhi   19
     89#define xcontext  20
     90#define rdebug    23
     91#define depc      24
     92#define eepc      30
    9393
    94 #endif /* KERN_mips32_REGNAME_H_ */
     94#endif
    9595
    9696/** @}

  • kernel/arch/mips32/include/atomic.h

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup mips32 
     29/** @addtogroup mips32
    3030 * @{
    3131 */
    … …  
    3535#ifndef KERN_mips32_ATOMIC_H_
    3636#define KERN_mips32_ATOMIC_H_
     37
     38#include <trace.h>
    3739
    3840#define atomic_inc(x)  ((void) atomic_add(x, 1))
    … …  
    5153 *
    5254 * @return Value after addition.
     55 *
    5356 */
    54 static inline long atomic_add(atomic_t *val, int i)
     57NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val,
     58    atomic_count_t i)
    5559{
    56         long tmp, v;
     60        atomic_count_t tmp;
     61        atomic_count_t v;
    5762       
    5863        asm volatile (
    … …  
    6469                "       beq %0, %4, 1b\n"   /* if the atomic operation failed, try again */
    6570                "       nop\n"
    66                 : "=&r" (tmp), "+m" (val->count), "=&r" (v)
    67                 : "r" (i), "i" (0)
     71                : "=&r" (tmp),
     72                  "+m" (val->count),
     73                  "=&r" (v)
     74                : "r" (i),
     75                  "i" (0)
    6876        );
    6977       
    … …  
    7179}
    7280
    73 static inline uint32_t test_and_set(atomic_t *val) {
    74         uint32_t tmp, v;
     81NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val)
     82{
     83        atomic_count_t tmp;
     84        atomic_count_t v;
    7585       
    7686        asm volatile (
    … …  
    8292                "       beqz %0, 1b\n"
    8393                "2:\n"
    84                 : "=&r" (tmp), "+m" (val->count), "=&r" (v)
     94                : "=&r" (tmp),
     95                  "+m" (val->count),
     96                  "=&r" (v)
    8597                : "i" (1)
    8698        );
    … …  
    89101}
    90102
    91 static inline void atomic_lock_arch(atomic_t *val) {
     103NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
     104{
    92105        do {
    93                 while (val->count)
    94                         ;
     106                while (val->count);
    95107        } while (test_and_set(val));
    96108}

  • kernel/arch/mips32/include/barrier.h

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup mips32 
     29/** @addtogroup mips32
    3030 * @{
    3131 */
    … …  
    3939 * TODO: implement true MIPS memory barriers for macros below.
    4040 */
    41 #define CS_ENTER_BARRIER()      asm volatile ("" ::: "memory")
    42 #define CS_LEAVE_BARRIER()      asm volatile ("" ::: "memory")
     41#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
     42#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
    4343
    44 #define memory_barrier()        asm volatile ("" ::: "memory")
    45 #define read_barrier()          asm volatile ("" ::: "memory")
    46 #define write_barrier()         asm volatile ("" ::: "memory")
     44#define memory_barrier() asm volatile ("" ::: "memory")
     45#define read_barrier()   asm volatile ("" ::: "memory")
     46#define write_barrier()  asm volatile ("" ::: "memory")
    4747
    4848#define smc_coherence(a)

  • kernel/arch/mips32/include/context.h

    rfb150d78 r46c20c8  
    4646#ifndef __ASM__
    4747
    48 #include <arch/types.h>
     48#include <typedefs.h>
    4949
    5050#define context_set(ctx, pc, stack, size) \

  • kernel/arch/mips32/include/context_offset.h

    rfb150d78 r46c20c8  
    6060# define OFFSET_F30     0x5c
    6161#endif /* KERNEL */
    62 
    63 /* istate_t */
    64 #define EOFFSET_AT     0x0
    65 #define EOFFSET_V0     0x4
    66 #define EOFFSET_V1     0x8
    67 #define EOFFSET_A0     0xc
    68 #define EOFFSET_A1     0x10
    69 #define EOFFSET_A2     0x14
    70 #define EOFFSET_A3     0x18
    71 #define EOFFSET_T0     0x1c
    72 #define EOFFSET_T1     0x20
    73 #define EOFFSET_T2     0x24
    74 #define EOFFSET_T3     0x28
    75 #define EOFFSET_T4     0x2c
    76 #define EOFFSET_T5     0x30
    77 #define EOFFSET_T6     0x34
    78 #define EOFFSET_T7     0x38
    79 #define EOFFSET_T8     0x3c
    80 #define EOFFSET_T9     0x40
    81 #define EOFFSET_GP     0x44
    82 #define EOFFSET_SP     0x48
    83 #define EOFFSET_RA     0x4c
    84 #define EOFFSET_LO     0x50
    85 #define EOFFSET_HI     0x54
    86 #define EOFFSET_STATUS 0x58
    87 #define EOFFSET_EPC    0x5c
    88 #define EOFFSET_K1     0x60
    89 #define REGISTER_SPACE 104      /* respect stack alignment */
    9062
    9163#ifdef __ASM__

  • kernel/arch/mips32/include/cp0.h

    rfb150d78 r46c20c8  
    3636#define KERN_mips32_CP0_H_
    3737
    38 #include <arch/types.h>
     38#ifdef KERNEL
     39#include <typedefs.h>
     40#else
     41#include <sys/types.h>
     42#endif
    3943
    40 #define cp0_status_ie_enabled_bit       (1 << 0)
    41 #define cp0_status_exl_exception_bit    (1 << 1)
    42 #define cp0_status_erl_error_bit        (1 << 2)
    43 #define cp0_status_um_bit               (1 << 4)
    44 #define cp0_status_bev_bootstrap_bit    (1 << 22)
    45 #define cp0_status_fpu_bit              (1 << 29)
     44#define cp0_status_ie_enabled_bit     (1 << 0)
     45#define cp0_status_exl_exception_bit  (1 << 1)
     46#define cp0_status_erl_error_bit      (1 << 2)
     47#define cp0_status_um_bit             (1 << 4)
     48#define cp0_status_bev_bootstrap_bit  (1 << 22)
     49#define cp0_status_fpu_bit            (1 << 29)
    4650
    4751#define cp0_status_im_shift             8

  • kernel/arch/mips32/include/cpu.h

    rfb150d78 r46c20c8  
    3636#define KERN_mips32_CPU_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939#include <arch/asm.h>
    4040

  • kernel/arch/mips32/include/cycle.h

    rfb150d78 r46c20c8  
    3838#include <arch/cp0.h>
    3939#include <arch/interrupt.h>
     40#include <trace.h>
    4041
    41 static inline uint64_t get_cycle(void)
     42NO_TRACE static inline uint64_t get_cycle(void)
    4243{
    4344        return ((uint64_t) count_hi << 32) + ((uint64_t) cp0_count_read());

  • kernel/arch/mips32/include/debug.h

    rfb150d78 r46c20c8  
    3636#define KERN_mips23_DEBUG_H_
    3737
    38 /**     simulator enters the trace mode */
    39 #define ___traceon()    asm volatile ( "\t.word\t0x39\n");
    40 /**     simulator leaves the trace mode */
    41 #define ___traceoff()   asm volatile ( "\t.word\t0x3d\n");
    42 /**     register dump */
    43 #define ___regview()    asm volatile ( "\t.word\t0x37\n");
    44 /**     halt the simulator */
    45 #define ___halt()       asm volatile ( "\t.word\t0x28\n");
    46 /**     simulator enters interactive mode */
    47 #define ___intmode()    asm volatile ( "\t.word\t0x29\n");
     38/** Enter the simulator trace mode */
     39#define ___traceon()  asm volatile ( "\t.word\t0x39\n");
     40
     41/** Leave the simulator trace mode */
     42#define ___traceoff()  asm volatile ( "\t.word\t0x3d\n");
     43
     44/** Ask the simulator to dump registers */
     45#define ___regview()  asm volatile ( "\t.word\t0x37\n");
     46
     47/** Halt the simulator */
     48#define ___halt()  asm volatile ( "\t.word\t0x28\n");
     49
     50/** Enter the simulator interactive mode */
     51#define ___intmode()  asm volatile ( "\t.word\t0x29\n");
    4852
    4953#endif

  • kernel/arch/mips32/include/debugger.h

    rfb150d78 r46c20c8  
    3737
    3838#include <arch/exception.h>
    39 #include <arch/types.h>
     39#include <typedefs.h>
    4040
    4141#define BKPOINTS_MAX 10
    4242
    43 #define BKPOINT_INPROG   (1 << 0)   /**< Breakpoint was shot */
    44 #define BKPOINT_ONESHOT  (1 << 1)   /**< One-time breakpoint,mandatory for j/b
    45                                          instructions */
    46 #define BKPOINT_REINST   (1 << 2)   /**< Breakpoint is set on the next
    47                                          instruction, so that it could be
    48                                          reinstalled on the previous one */
    49 #define BKPOINT_FUNCCALL (1 << 3)   /**< Call a predefined function */
     43/** Breakpoint was shot */
     44#define BKPOINT_INPROG  (1 << 0)
     45
     46/** One-time breakpoint, mandatory for j/b instructions */
     47#define BKPOINT_ONESHOT  (1 << 1)
     48
     49/**
     50 * Breakpoint is set on the next instruction, so that it
     51 * could be reinstalled on the previous one
     52 */
     53#define BKPOINT_REINST  (1 << 2)
     54
     55/** Call a predefined function */
     56#define BKPOINT_FUNCCALL  (1 << 3)
     57
    5058
    5159typedef struct  {
    52         uintptr_t address;      /**< Breakpoint address */
    53         unative_t instruction; /**< Original instruction */
     60        uintptr_t address;          /**< Breakpoint address */
     61        unative_t instruction;      /**< Original instruction */
    5462        unative_t nextinstruction;  /**< Original instruction following break */
    55         int flags;        /**< Flags regarding breakpoint */
     63        unsigned int flags;         /**< Flags regarding breakpoint */
    5664        size_t counter;
    57         void (*bkfunc)(void *b, istate_t *istate);
     65        void (*bkfunc)(void *, istate_t *);
    5866} bpinfo_t;
    5967
     68extern bpinfo_t breakpoints[BKPOINTS_MAX];
     69
     70extern bool is_jump(unative_t);
     71
    6072extern void debugger_init(void);
    61 void debugger_bpoint(istate_t *istate);
    62 
    63 extern bpinfo_t breakpoints[BKPOINTS_MAX];
     73extern void debugger_bpoint(istate_t *);
    6474
    6575#endif

  • kernel/arch/mips32/include/exception.h

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup mips32 
     29/** @addtogroup mips32
    3030 * @{
    3131 */
    … …  
    3636#define KERN_mips32_EXCEPTION_H_
    3737
    38 #include <arch/types.h>
    39 #include <arch/cp0.h>
     38#include <typedefs.h>
     39#include <arch/istate.h>
    4040
    41 #define EXC_Int         0
    42 #define EXC_Mod         1
    43 #define EXC_TLBL        2
    44 #define EXC_TLBS        3
    45 #define EXC_AdEL        4
    46 #define EXC_AdES        5
    47 #define EXC_IBE         6
    48 #define EXC_DBE         7
    49 #define EXC_Sys         8
    50 #define EXC_Bp          9
    51 #define EXC_RI          10
    52 #define EXC_CpU         11
    53 #define EXC_Ov          12
    54 #define EXC_Tr          13
    55 #define EXC_VCEI        14
    56 #define EXC_FPE         15
    57 #define EXC_WATCH       23
    58 #define EXC_VCED        31
    59 
    60 typedef struct istate {
    61         uint32_t at;
    62         uint32_t v0;
    63         uint32_t v1;
    64         uint32_t a0;
    65         uint32_t a1;
    66         uint32_t a2;
    67         uint32_t a3;
    68         uint32_t t0;
    69         uint32_t t1;
    70         uint32_t t2;
    71         uint32_t t3;
    72         uint32_t t4;
    73         uint32_t t5;
    74         uint32_t t6;
    75         uint32_t t7;
    76         uint32_t t8;
    77         uint32_t t9;
    78         uint32_t gp;
    79         uint32_t sp;
    80         uint32_t ra;
    81        
    82         uint32_t lo;
    83         uint32_t hi;
    84 
    85         uint32_t status; /* cp0_status */
    86         uint32_t epc; /* cp0_epc */
    87         uint32_t k1; /* We use it as thread-local pointer */
    88 } istate_t;
    89 
    90 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
    91 {
    92         istate->epc = retaddr;
    93 }
    94 
    95 /** Return true if exception happened while in userspace */
    96 static inline int istate_from_uspace(istate_t *istate)
    97 {
    98         return istate->status & cp0_status_um_bit;
    99 }
    100 static inline unative_t istate_get_pc(istate_t *istate)
    101 {
    102         return istate->epc;
    103 }
    104 static inline unative_t istate_get_fp(istate_t *istate)
    105 {
    106         return 0;       /* FIXME */
    107 }
     41#define EXC_Int    0
     42#define EXC_Mod    1
     43#define EXC_TLBL   2
     44#define EXC_TLBS   3
     45#define EXC_AdEL   4
     46#define EXC_AdES   5
     47#define EXC_IBE    6
     48#define EXC_DBE    7
     49#define EXC_Sys    8
     50#define EXC_Bp     9
     51#define EXC_RI     10
     52#define EXC_CpU    11
     53#define EXC_Ov     12
     54#define EXC_Tr     13
     55#define EXC_VCEI   14
     56#define EXC_FPE    15
     57#define EXC_WATCH  23
     58#define EXC_VCED   31
    10859
    10960extern void exception(istate_t *istate);

  • kernel/arch/mips32/include/faddr.h

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup mips32 
     29/** @addtogroup mips32
    3030 * @{
    3131 */
    … …  
    3636#define KERN_mips32_FADDR_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939
    40 #define FADDR(fptr)             ((uintptr_t) (fptr))
     40#define FADDR(fptr)  ((uintptr_t) (fptr))
    4141
    4242#endif

  • kernel/arch/mips32/include/fpu_context.h

    rfb150d78 r46c20c8  
    3636#define KERN_mips32_FPU_CONTEXT_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939
    4040#define FPU_CONTEXT_ALIGN    sizeof(unative_t)

  • kernel/arch/mips32/include/memstr.h

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup mips32 
     29/** @addtogroup mips32
    3030 * @{
    3131 */
    … …  
    3838#define memcpy(dst, src, cnt)  __builtin_memcpy((dst), (src), (cnt))
    3939
    40 extern void memsetw(void *dst, size_t cnt, uint16_t x);
    41 extern void memsetb(void *dst, size_t cnt, uint8_t x);
    42 
    43 extern int memcmp(const void *a, const void *b, size_t cnt);
     40extern void memsetw(void *, size_t, uint16_t);
     41extern void memsetb(void *, size_t, uint8_t);
    4442
    4543#endif

  • kernel/arch/mips32/include/mm/as.h

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup mips32mm       
     29/** @addtogroup mips32mm
    3030 * @{
    3131 */
    … …  
    3636#define KERN_mips32_AS_H_
    3737
    38 #define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH      0
     38#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH  0
    3939
    4040#define KERNEL_ADDRESS_SPACE_START_ARCH         (unsigned long) 0x80000000

  • kernel/arch/mips32/include/mm/asid.h

    rfb150d78 r46c20c8  
    3636#define KERN_mips32_ASID_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939
    4040#define ASID_MAX_ARCH  255    /* 2^8 - 1 */

  • kernel/arch/mips32/include/mm/page.h

    rfb150d78 r46c20c8  
    3737
    3838#include <arch/mm/frame.h>
     39#include <trace.h>
    3940
    4041#define PAGE_WIDTH      FRAME_WIDTH
    … …  
    155156
    156157
    157 static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
     158NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
    158159{
    159160        pte_t *p = &pt[i];
    … …  
    168169}
    169170
    170 static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
     171NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
    171172{
    172173        pte_t *p = &pt[i];

  • kernel/arch/mips32/include/mm/tlb.h

    rfb150d78 r46c20c8  
    3636#define KERN_mips32_TLB_H_
    3737
    38 #include <arch/types.h>
    3938#include <typedefs.h>
    4039#include <arch/mm/asid.h>
    4140#include <arch/exception.h>
     41#include <trace.h>
    4242
    4343#define TLB_ENTRY_COUNT  48
    … …  
    127127 * Probe TLB for Matching Entry.
    128128 */
    129 static inline void tlbp(void)
     129NO_TRACE static inline void tlbp(void)
    130130{
    131131        asm volatile ("tlbp\n\t");
    … …  
    137137 * Read Indexed TLB Entry.
    138138 */
    139 static inline void tlbr(void)
     139NO_TRACE static inline void tlbr(void)
    140140{
    141141        asm volatile ("tlbr\n\t");
    … …  
    146146 * Write Indexed TLB Entry.
    147147 */
    148 static inline void tlbwi(void)
     148NO_TRACE static inline void tlbwi(void)
    149149{
    150150        asm volatile ("tlbwi\n\t");
    … …  
    155155 * Write Random TLB Entry.
    156156 */
    157 static inline void tlbwr(void)
     157NO_TRACE static inline void tlbwr(void)
    158158{
    159159        asm volatile ("tlbwr\n\t");

  • kernel/arch/mips32/include/smp/dorder.h

    rfb150d78 r46c20c8  
    2727 */
    2828
     29/** @addtogroup mips32
     30 * @{
     31 */
     32/** @file
     33 */
     34
    2935#ifndef KERN_mips32_DORDER_H_
    3036#define KERN_mips32_DORDER_H_
    3137
    32 extern void ipi_broadcast_arch(int ipi);
     38#include <typedefs.h>
     39
     40extern uint32_t dorder_cpuid(void);
     41extern void dorder_ipi_ack(uint32_t);
    3342
    3443#endif
     44
     45/** @}
     46 */

  • kernel/arch/mips32/include/types.h

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup mips32 
     29/** @addtogroup mips32
    3030 * @{
    3131 */
    … …  
    3535#ifndef KERN_mips32_TYPES_H_
    3636#define KERN_mips32_TYPES_H_
    37 
    38 typedef signed char int8_t;
    39 typedef signed short int16_t;
    40 typedef signed long int32_t;
    41 typedef signed long long int64_t;
    42 
    43 typedef unsigned char uint8_t;
    44 typedef unsigned short uint16_t;
    45 typedef unsigned long uint32_t;
    46 typedef unsigned long long uint64_t;
    4737
    4838typedef uint32_t size_t;
    … …  
    5545typedef uint32_t unative_t;
    5646typedef int32_t native_t;
     47typedef uint32_t atomic_count_t;
    5748
    5849typedef struct {
    5950} fncptr_t;
    6051
    61 #define PRIp "x"        /**< Format for uintptr_t. */
    62 #define PRIs "u"        /**< Format for size_t. */
     52#define INTN_C(c)   INT32_C(c)
     53#define UINTN_C(c)  UINT32_C(c)
    6354
    64 #define PRId8 "d"       /**< Format for int8_t. */
    65 #define PRId16 "d"      /**< Format for int16_t. */
    66 #define PRId32 "ld"     /**< Format for int32_t. */
    67 #define PRId64 "lld"    /**< Format for int64_t. */
    68 #define PRIdn "d"       /**< Format for native_t. */
    69 
    70 #define PRIu8 "u"       /**< Format for uint8_t. */
    71 #define PRIu16 "u"      /**< Format for uint16_t. */
    72 #define PRIu32 "u"      /**< Format for uint32_t. */
    73 #define PRIu64 "llu"    /**< Format for uint64_t. */
    74 #define PRIun "u"       /**< Format for unative_t. */
    75 
    76 #define PRIx8 "x"       /**< Format for hexadecimal (u)int8_t. */
    77 #define PRIx16 "x"      /**< Format for hexadecimal (u)int16_t. */
    78 #define PRIx32 "x"      /**< Format for hexadecimal (u)uint32_t. */
    79 #define PRIx64 "llx"    /**< Format for hexadecimal (u)int64_t. */
    80 #define PRIxn "x"       /**< Format for hexadecimal (u)native_t. */
     55#define PRIdn  PRId32  /**< Format for native_t. */
     56#define PRIun  PRIu32  /**< Format for unative_t. */
     57#define PRIxn  PRIx32  /**< Format for hexadecimal unative_t. */
     58#define PRIua  PRIu32  /**< Format for atomic_count_t. */
    8159
    8260#endif
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