Changeset 3fafe5e0 in mainline for uspace/drv/bus/usb/xhci/hw_struct/trb.h
- Timestamp:
- 2018-04-27T14:15:03Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 7148abf
- Parents:
- a2eb85d
- git-author:
- Jiri Svoboda <jiri@…> (2018-04-26 17:14:26)
- git-committer:
- Jiri Svoboda <jiri@…> (2018-04-27 14:15:03)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/xhci/hw_struct/trb.h
ra2eb85d r3fafe5e0 48 48 XHCI_TRB_TYPE_RESERVED = 0, 49 49 50 // Transfer ring: 50 /* 51 * Transfer ring: 52 */ 51 53 XHCI_TRB_TYPE_NORMAL, 52 54 XHCI_TRB_TYPE_SETUP_STAGE, … … 58 60 XHCI_TRB_TYPE_NO_OP, 59 61 60 // Command ring: 62 /* 63 * Command ring: 64 */ 61 65 XHCI_TRB_TYPE_ENABLE_SLOT_CMD, 62 66 XHCI_TRB_TYPE_DISABLE_SLOT_CMD, … … 74 78 XHCI_TRB_TYPE_FORCE_HEADER_CMD, 75 79 XHCI_TRB_TYPE_NO_OP_CMD, 76 // Reserved: 24-31 77 78 // Event ring: 80 /* 81 * Reserved: 24-31 82 */ 83 84 /* 85 * Event ring: 86 */ 79 87 XHCI_TRB_TYPE_TRANSFER_EVENT = 32, 80 88 XHCI_TRB_TYPE_COMMAND_COMPLETION_EVENT,
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