Changeset 3e828ea in mainline for boot/arch/arm32/src/asm.S

Timestamp:

2019-09-23T12:49:29Z (7 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

9be2358

Parents:

9259d20 (diff), 1a4ec93f (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

git-author:

Jiri Svoboda <jiri@…> (2019-09-22 12:49:07)

git-committer:

Jiri Svoboda <jiri@…> (2019-09-23 12:49:29)

Message:

Merge changes from master, especially Meson build

File:

• boot/arch/arm32/src/asm.S (modified) (2 diffs)

boot/arch/arm32/src/asm.S

@@ -32 +32 @@
 .section BOOTSTRAP
 
+#define CP15_C1_U               22
+#define CP15_C1_IC              12
+#define CP15_C1_BP              11
+#define CP15_C1_DC              2
+
 SYMBOL(start)
+
+#ifdef PROCESSOR_ARCH_armv6
+        /*
+         * Enable unaligned doubleword memory accesses (STRD/LDRD) if the
+         * processor supports it. Note that that boils down to ARMv6 processors
+         * only as the older architectures require doubleword alignment and
+         * ARMv7 always assumes the U bit is 1.
+         */
+        mrc     p15, 0, r0, c1, c0, 0
+        orr     r0, r0, #(1 << CP15_C1_U)
+        mcr     p15, 0, r0, c1, c0, 0
+#endif
+
         ldr sp, =boot_stack
         b bootstrap
@@ -59 +77 @@
         # r0 is kernel entry point
         # r1 is pointer to the bootinfo structure
-
-#define CP15_C1_IC              12
-#define CP15_C1_BP              11
-#define CP15_C1_DC              2
-
 
 #ifndef PROCESSOR_ARCH_armv7_a