Changeset 3bacee1 in mainline for boot/arch/arm32/src/mm.c

Timestamp:

2018-04-12T16:27:17Z (7 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

3cf22f9

Parents:

76d0981d

git-author:

Jiri Svoboda <jiri@…> (2018-04-11 19:25:33)

git-committer:

Jiri Svoboda <jiri@…> (2018-04-12 16:27:17)

Message:

Make ccheck-fix again and commit more good files.

File:

• boot/arch/arm32/src/mm.c (modified) (7 diffs)

boot/arch/arm32/src/mm.c

@@ -43 +43 @@
 {
         unsigned log = 0;
-        while (val >> log++);
+        while (val >> log++)
+                ;
         return log - 2;
 }
@@ -70 +71 @@
         const uint32_t cinfo = CLIDR_read();
         for (unsigned i = 0; i < 7; ++i) {
-                switch (CLIDR_CACHE(i, cinfo))
-                {
+                switch (CLIDR_CACHE(i, cinfo)) {
                 case CLIDR_DCACHE_ONLY:
                 case CLIDR_SEP_CACHE:
@@ -78 +78 @@
                 }
         }
-        asm volatile ( "dsb\n" );
+        asm volatile ("dsb\n");
         ICIALLU_write(0);
-        asm volatile ( "isb\n" );
+        asm volatile ("isb\n");
 }
 #endif
@@ -88 +88 @@
 {
         asm volatile (
-                "mrc p15, 0, r0, c1, c0, 0\n"
-                "bic r0, r0, #1\n"
-                "mcr p15, 0, r0, c1, c0, 0\n"
-                ::: "r0"
+            "mrc p15, 0, r0, c1, c0, 0\n"
+            "bic r0, r0, #1\n"
+            "mcr p15, 0, r0, c1, c0, 0\n"
+            ::: "r0"
         );
 }
@@ -135 +135 @@
  *
  */
-static void init_ptl0_section(pte_level0_section_t* pte,
+static void init_ptl0_section(pte_level0_section_t *pte,
     pfn_t frame)
 {
@@ -204 +204 @@
         asm volatile (
                 /* Behave as a client of domains */
-                "ldr r0, =0x55555555\n"
-                "mcr p15, 0, r0, c3, c0, 0\n"
+            "ldr r0, =0x55555555\n"
+            "mcr p15, 0, r0, c3, c0, 0\n"
 
                 /* Current settings */
-                "mrc p15, 0, r0, c1, c0, 0\n"
+            "mrc p15, 0, r0, c1, c0, 0\n"
 
                 /* Enable ICache, DCache, BPredictors and MMU,
@@ -217 +217 @@
                  */
 #ifdef PROCESSOR_ARCH_armv6
-                "ldr r1, =0x00801805\n"
+            "ldr r1, =0x00801805\n"
 #else
-                "ldr r1, =0x00001805\n"
-#endif
-
-                "orr r0, r0, r1\n"
+            "ldr r1, =0x00001805\n"
+#endif
+
+            "orr r0, r0, r1\n"
 
                 /* Invalidate the TLB content before turning on the MMU.
                  * ARMv7-A Reference manual, B3.10.3
                  */
-                "mcr p15, 0, r0, c8, c7, 0\n"
+            "mcr p15, 0, r0, c8, c7, 0\n"
 
                 /* Store settings, enable the MMU */
-                "mcr p15, 0, r0, c1, c0, 0\n"
-                ::: "r0", "r1"
+            "mcr p15, 0, r0, c1, c0, 0\n"
+            ::: "r0", "r1"
         );
 }