Changeset 38de8a5 in mainline for arch/mips/src/interrupt.c

Timestamp:

2005-09-09T13:50:54Z (20 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

b02e5d1

Parents:

b0edf3b2

Message:

MIPS architecture now works without any problems in

• msim: compile as OUTPUT_FORMAT(binary)
• gxemul: compile as OUTPUT_FORMAT(ecoff-littlemips), or create

configuration file for binary format (will be done later)

• simics: compile as OUTPUT_FORMAT(elf32-little), might work with binary

format, didn't try yet.

File:

• arch/mips/src/interrupt.c (modified) (2 diffs)

arch/mips/src/interrupt.c

@@ -58 +58 @@
 }
 
-
 void interrupt(void)
 {
@@ -84 +83 @@
                                         break;
                                 case 7: /* Timer Interrupt */
-                                        cp0_compare_write(cp0_compare_value); /* clear timer interrupt */
+                                        cp0_compare_write(cp0_count_read() + cp0_compare_value); /* clear timer interrupt */
                                         /* start counting over again */
-                                        cp0_count_write(0);
                                         clock();
                                         break;