Changeset 38dc82d in mainline for kernel/arch/mips32/src/mm/tlb.c
- Timestamp:
- 2016-08-31T14:16:45Z (9 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 346b12a2
- Parents:
- dc05a9a
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/mips32/src/mm/tlb.c
rdc05a9a r38dc82d 97 97 entry_lo_t lo; 98 98 uintptr_t badvaddr; 99 pte_t *pte;99 pte_t pte; 100 100 101 101 badvaddr = cp0_badvaddr_read(); 102 102 103 pte = page_mapping_find(AS, badvaddr, true);104 if ( pte && pte->p) {103 bool found = page_mapping_find(AS, badvaddr, true, &pte); 104 if (found && pte.p) { 105 105 /* 106 106 * Record access to PTE. 107 107 */ 108 pte ->a = 1;109 110 tlb_prepare_entry_lo(&lo, pte ->g, pte->p, pte->d,111 pte ->cacheable, pte->pfn);108 pte.a = 1; 109 110 tlb_prepare_entry_lo(&lo, pte.g, pte.p, pte.d, 111 pte.cacheable, pte.pfn); 112 112 113 113 /* … … 138 138 tlb_index_t index; 139 139 uintptr_t badvaddr; 140 pte_t *pte;140 pte_t pte; 141 141 142 142 /* … … 162 162 badvaddr = cp0_badvaddr_read(); 163 163 164 pte = page_mapping_find(AS, badvaddr, true);165 if ( pte && pte->p) {164 bool found = page_mapping_find(AS, badvaddr, true, &pte); 165 if (found && pte.p) { 166 166 /* 167 167 * Read the faulting TLB entry. … … 172 172 * Record access to PTE. 173 173 */ 174 pte ->a = 1;175 176 tlb_prepare_entry_lo(&lo, pte ->g, pte->p, pte->d,177 pte ->cacheable, pte->pfn);174 pte.a = 1; 175 176 tlb_prepare_entry_lo(&lo, pte.g, pte.p, pte.d, 177 pte.cacheable, pte.pfn); 178 178 179 179 /* … … 200 200 tlb_index_t index; 201 201 uintptr_t badvaddr; 202 pte_t *pte;202 pte_t pte; 203 203 204 204 badvaddr = cp0_badvaddr_read(); … … 224 224 } 225 225 226 pte = page_mapping_find(AS, badvaddr, true);227 if ( pte && pte->p && pte->w) {226 bool found = page_mapping_find(AS, badvaddr, true, &pte); 227 if (found && pte.p && pte.w) { 228 228 /* 229 229 * Read the faulting TLB entry. … … 234 234 * Record access and write to PTE. 235 235 */ 236 pte ->a = 1;237 pte ->d = 1;238 239 tlb_prepare_entry_lo(&lo, pte ->g, pte->p, pte->w,240 pte ->cacheable, pte->pfn);236 pte.a = 1; 237 pte.d = 1; 238 239 tlb_prepare_entry_lo(&lo, pte.g, pte.p, pte.w, 240 pte.cacheable, pte.pfn); 241 241 242 242 /*
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