Changeset 3412e844 in mainline for kernel/arch/arm32/src/cpu/cpu.c
- Timestamp:
- 2012-11-24T02:28:47Z (12 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f1e496a
- Parents:
- 6e634d6
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/arm32/src/cpu/cpu.c
r6e634d6 r3412e844 38 38 #include <arch.h> 39 39 #include <print.h> 40 #include <fpu_context.h> 40 41 41 42 /** Number of indexes left out in the #imp_data array */ … … 138 139 } 139 140 141 void fpu_init(void) 142 { 143 //TODO: Identify FPU unit 144 //and set correct functions to save/restore ctx 145 } 146 147 void fpu_enable(void) 148 { 149 /* Enable FPU instructions */ 150 asm volatile ( 151 "ldr r1, =0x40000000\n" 152 "vmsr fpexc, r1\n" 153 ::: "r1" 154 ); 155 } 156 157 void fpu_disable(void) 158 { 159 /* Disable FPU instructions */ 160 asm volatile ( 161 "ldr r1, =0x00000000\n" 162 "vmsr fpexc, r1\n" 163 ::: "r1" 164 ); 165 } 166 167 void fpu_context_save(fpu_context_t *ctx) 168 { 169 // TODO check and complete. What about fpexc? 170 asm volatile ( 171 "vmrs r1, fpscr\n" 172 // "vmrs r2, fpexc\n" 173 "stm %0, {r1, r2}\n" 174 "vstm %0, {d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15}\n" 175 ::"r" (ctx): "r1","r2","memory" 176 ); 177 } 178 179 void fpu_context_restore(fpu_context_t *ctx) 180 { 181 // TODO check and complete. What about fpexc? 182 asm volatile ( 183 "ldm %0, {r1, r2}\n" 184 "vmsr fpscr, r1\n" 185 // "vmsr fpexc, r2\n" 186 "vldm %0, {d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15}\n" 187 ::"r" (ctx): "r1","r2" 188 ); 189 } 190 140 191 /** Retrieves processor identification and stores it to #CPU.arch */ 141 192 void cpu_identify(void)
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