Changeset 33d394a in mainline for kernel/arch/arm32/include/barrier.h


Ignore:
Timestamp:
2013-01-20T17:41:12Z (12 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
297fda2c
Parents:
9a5ccc14
Message:

arm32: Implement smc_coherence.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/include/barrier.h

    r9a5ccc14 r33d394a  
    3737#define KERN_arm32_BARRIER_H_
    3838
    39 /*
    40  * TODO: implement true ARM memory barriers for macros below.
    41  * ARMv6 introduced user access of the following commands:
    42  * • Prefetch flush
    43  * • Data synchronization barrier
    44  * • Data memory barrier
    45  * • Clean and prefetch range operations.
    46  * ARM Architecture Reference Manual version I ch. B.3.2.1 p. B3-4
    47  */
     39#ifdef KERNEL
     40#include <arch/cp15.h>
     41#else
     42#include <libarch/cp15.h>
     43#endif
     44
    4845#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
    4946#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
     
    6057#define read_barrier()    asm volatile ("dsb" ::: "memory")
    6158#define write_barrier()   asm volatile ("dsb st" ::: "memory")
    62 #elif defined PROCESSOR_ARCH_armv6
     59#define inst_barrier()    asm volatile ("isb" ::: "memory")
     60#elif defined PROCESSOR_ARCH_armv6 | defined KERNEL
     61/*
     62 * ARMv6 introduced user access of the following commands:
     63 * - Prefetch flush
     64 * - Data synchronization barrier
     65 * - Data memory barrier
     66 * - Clean and prefetch range operations.
     67 * ARM Architecture Reference Manual version I ch. B.3.2.1 p. B3-4
     68 */
    6369/* ARMv6- use system control coprocessor (CP15) for memory barrier instructions.
    6470 * Although at least mcr p15, 0, r0, c7, c10, 4 is mentioned in earlier archs,
    6571 * CP15 implementation is mandatory only for armv6+.
    6672 */
    67 #define memory_barrier()  asm volatile ("ldr r0, =0\nmcr p15, 0, r0, c7, c10, 5" ::: "r0", "memory")
    68 #define read_barrier()    asm volatile ("ldr r0, =0\nmcr p15, 0, r0, c7, c10, 4" ::: "r0", "memory")
     73#define memory_barrier()  CP15DMB_write(0)
     74#define read_barrier()    CP15DSB_write(0)
    6975#define write_barrier()   read_barrier()
     76#define inst_barrier()    CP15ISB_write(0)
    7077#else
    7178/* Older manuals mention syscalls as a way to implement cache coherency and
     
    7380 * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28)
    7481 */
    75 // TODO implement on per PROCESSOR basis
     82// TODO implement on per PROCESSOR basis or via syscalls
    7683#define memory_barrier()  asm volatile ("" ::: "memory")
    7784#define read_barrier()    asm volatile ("" ::: "memory")
    7885#define write_barrier()   asm volatile ("" ::: "memory")
     86#define inst_barrier()    asm volatile ("" ::: "memory")
    7987#endif
    8088
     
    94102 */
    95103
    96 #ifdef PROCESSOR_ARCH_armv7_a
    97 #define smc_coherence(a) asm volatile ( "isb" ::: "memory")
    98 #define smc_coherence_block(a, l) smc_coherence(a)
    99 #else
     104#if defined PROCESSOR_ARCH_armv7_a | defined PROCESSOR_ARCH_armv6 | defined KERNEL
    100105/* Available on all supported arms,
    101106 * invalidates entire ICache so the written value does not matter. */
    102107//TODO might be PL1 only on armv5 -
    103 #define smc_coherence(a) asm volatile ( "mcr p15, 0, r0, c7, c5, 0")
     108#define smc_coherence(a) \
     109do { \
     110        DCCMVAU_write((uint32_t)(a));  /* Write changed memory */\
     111        write_barrier();             /* Wait for completion */\
     112        ICIALLU_write(0);            /* Flush ICache */\
     113        inst_barrier();              /* Wait for Inst refetch */\
     114} while (0)
     115// TODO: Implement blocks
     116#define smc_coherence_block(a, l) smc_coherence(a)
     117#else
     118#define smc_coherence(a)
    104119#define smc_coherence_block(a, l) smc_coherence(a)
    105120#endif
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