Changeset 2d0c3a6 in mainline
- Timestamp:
- 2010-08-12T20:50:50Z (14 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- ddd7118
- Parents:
- ff586e06 (diff), 527298a (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)
links above to see all the changes relative to each parent. - Files:
-
- 3 added
- 8 edited
Legend:
- Unmodified
- Added
- Removed
-
boot/arch/arm32/Makefile.inc
rff586e06 r2d0c3a6 42 42 43 43 RD_SRVS_ESSENTIAL += \ 44 $(USPACE_PATH)/srv/hid/s3c24xx_ts/s3c24ts \ 44 45 $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24ser 45 46 -
kernel/arch/arm32/src/mach/gta02/gta02.c
rff586e06 r2d0c3a6 221 221 } 222 222 } 223 224 /* Enable interrupts from ADC */ 225 s3c24xx_irqc_src_enable(>a02_irqc, S3C24XX_INT_ADC); 226 227 /* Enable interrupts from ADC sub-sources */ 228 s3c24xx_irqc_subsrc_enable(>a02_irqc, S3C24XX_SUBINT_ADC_S); 229 s3c24xx_irqc_subsrc_enable(>a02_irqc, S3C24XX_SUBINT_TC); 223 230 } 224 231 -
kernel/genarch/include/drivers/s3c24xx_uart/s3c24xx_uart.h
rff586e06 r2d0c3a6 60 60 } s3c24xx_uart_io_t; 61 61 62 /* Bits in UTRSTAT register */ 63 #define S3C24XX_UTRSTAT_TX_EMPTY 0x4 64 #define S3C24XX_UTRSTAT_RDATA 0x1 65 66 /* Bits in UFSTAT register */ 67 #define S3C24XX_UFSTAT_TX_FULL 0x4000 68 #define S3C24XX_UFSTAT_RX_FULL 0x0040 69 #define S3C24XX_UFSTAT_RX_COUNT 0x002f 70 71 /* Bits in UCON register */ 72 #define UCON_RX_INT_LEVEL 0x100 73 74 /* Bits in UFCON register */ 75 #define UFCON_TX_FIFO_TLEVEL_EMPTY 0x00 76 #define UFCON_RX_FIFO_TLEVEL_1B 0x00 77 #define UFCON_FIFO_ENABLE 0x01 78 79 62 80 /** S3C24xx UART instance */ 63 81 typedef struct { -
kernel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c
rff586e06 r2d0c3a6 46 46 #include <sysinfo/sysinfo.h> 47 47 #include <str.h> 48 49 /* Bits in UTRSTAT register */50 #define S3C24XX_UTRSTAT_TX_EMPTY 0x451 #define S3C24XX_UTRSTAT_RDATA 0x152 53 #define S3C24XX_UFSTAT_TX_FULL 0x400054 #define S3C24XX_UFSTAT_RX_FULL 0x004055 #define S3C24XX_UFSTAT_RX_COUNT 0x002f56 48 57 49 static void s3c24xx_uart_sendb(outdev_t *dev, uint8_t byte) … … 129 121 130 122 /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */ 131 pio_write_32(&uart->io->ufcon, 0x01); 123 pio_write_32(&uart->io->ufcon, UFCON_FIFO_ENABLE | 124 UFCON_TX_FIFO_TLEVEL_EMPTY | UFCON_RX_FIFO_TLEVEL_1B); 132 125 133 126 /* Set RX interrupt to pulse mode */ 134 127 pio_write_32(&uart->io->ucon, 135 pio_read_32(&uart->io->ucon) & ~ (1 << 8));128 pio_read_32(&uart->io->ucon) & ~UCON_RX_INT_LEVEL); 136 129 137 130 if (!fb_exported) { -
uspace/Makefile
rff586e06 r2d0c3a6 66 66 srv/hid/adb_mouse \ 67 67 srv/hid/char_mouse \ 68 srv/hid/s3c24xx_ts \ 68 69 srv/hid/fb \ 69 70 srv/hid/kbd \ -
uspace/app/init/init.c
rff586e06 r2d0c3a6 277 277 srv_start("/srv/adb_ms"); 278 278 srv_start("/srv/char_ms"); 279 srv_start("/srv/s3c24ts"); 279 280 280 281 spawn("/srv/fb"); -
uspace/srv/hw/char/s3c24xx_uart/s3c24xx_uart.c
rff586e06 r2d0c3a6 53 53 #define NAME "s3c24ser" 54 54 #define NAMESPACE "char" 55 56 /* Bits in UTRSTAT register */57 #define S3C24XX_UTRSTAT_TX_EMPTY 0x458 #define S3C24XX_UTRSTAT_RDATA 0x159 60 /* Bits in UFSTAT register */61 #define S3C24XX_UFSTAT_TX_FULL 0x400062 #define S3C24XX_UFSTAT_RX_FULL 0x004063 #define S3C24XX_UFSTAT_RX_COUNT 0x002f64 55 65 56 static irq_cmd_t uart_irq_cmds[] = { … … 169 160 } 170 161 171 if (status & 0x0f)162 if (status != 0) 172 163 printf(NAME ": Error status 0x%x\n", status); 173 164 } … … 202 193 203 194 /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */ 204 pio_write_32(&uart->io->ufcon, 0x01); 195 pio_write_32(&uart->io->ufcon, UFCON_FIFO_ENABLE | 196 UFCON_TX_FIFO_TLEVEL_EMPTY | UFCON_RX_FIFO_TLEVEL_1B); 205 197 206 198 /* Set RX interrupt to pulse mode */ 207 199 pio_write_32(&uart->io->ucon, 208 pio_read_32(&uart->io->ucon) & ~ (1 << 8));200 pio_read_32(&uart->io->ucon) & ~UCON_RX_INT_LEVEL); 209 201 210 202 return EOK; -
uspace/srv/hw/char/s3c24xx_uart/s3c24xx_uart.h
rff586e06 r2d0c3a6 58 58 } s3c24xx_uart_io_t; 59 59 60 /* Bits in UTRSTAT register */ 61 #define S3C24XX_UTRSTAT_TX_EMPTY 0x4 62 #define S3C24XX_UTRSTAT_RDATA 0x1 63 64 /* Bits in UFSTAT register */ 65 #define S3C24XX_UFSTAT_TX_FULL 0x4000 66 #define S3C24XX_UFSTAT_RX_FULL 0x0040 67 #define S3C24XX_UFSTAT_RX_COUNT 0x002f 68 69 /* Bits in UCON register */ 70 #define UCON_RX_INT_LEVEL 0x100 71 72 /* Bits in UFCON register */ 73 #define UFCON_TX_FIFO_TLEVEL_EMPTY 0x00 74 #define UFCON_RX_FIFO_TLEVEL_1B 0x00 75 #define UFCON_FIFO_ENABLE 0x01 76 77 60 78 /** S3C24xx UART instance */ 61 79 typedef struct {
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