Changeset 2d0c3a6 in mainline for kernel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c
- Timestamp:
- 2010-08-12T20:50:50Z (14 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- ddd7118
- Parents:
- ff586e06 (diff), 527298a (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
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- 1 edited
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kernel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c
rff586e06 r2d0c3a6 46 46 #include <sysinfo/sysinfo.h> 47 47 #include <str.h> 48 49 /* Bits in UTRSTAT register */50 #define S3C24XX_UTRSTAT_TX_EMPTY 0x451 #define S3C24XX_UTRSTAT_RDATA 0x152 53 #define S3C24XX_UFSTAT_TX_FULL 0x400054 #define S3C24XX_UFSTAT_RX_FULL 0x004055 #define S3C24XX_UFSTAT_RX_COUNT 0x002f56 48 57 49 static void s3c24xx_uart_sendb(outdev_t *dev, uint8_t byte) … … 129 121 130 122 /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */ 131 pio_write_32(&uart->io->ufcon, 0x01); 123 pio_write_32(&uart->io->ufcon, UFCON_FIFO_ENABLE | 124 UFCON_TX_FIFO_TLEVEL_EMPTY | UFCON_RX_FIFO_TLEVEL_1B); 132 125 133 126 /* Set RX interrupt to pulse mode */ 134 127 pio_write_32(&uart->io->ucon, 135 pio_read_32(&uart->io->ucon) & ~ (1 << 8));128 pio_read_32(&uart->io->ucon) & ~UCON_RX_INT_LEVEL); 136 129 137 130 if (!fb_exported) {
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