Changeset 25eec4e in mainline for kernel/arch/amd64/src/fpu_context.c
- Timestamp:
- 2013-04-19T18:38:18Z (12 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 6d717a4
- Parents:
- a1e2df13 (diff), 289cb7dd (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
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- 1 edited
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kernel/arch/amd64/src/fpu_context.c
ra1e2df13 r25eec4e 57 57 { 58 58 /* TODO: Zero all SSE, MMX etc. registers */ 59 /* Default value of SCR register is 0x1f80, 60 * it masks all FPU exceptions*/ 59 61 asm volatile ( 60 62 "fninit\n"
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