Changeset 005b765 in mainline for kernel/arch/arm32/include/cp15.h

Timestamp:

2013-01-24T22:07:06Z (13 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

03362fbd, 3acd1bb, d59c046

Parents:

6218d4b (diff), 24bead17 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge arm improvements.

Speed up boot by enabling caches early (but disable before jumping to kernel).
Add cycle counters on armv7.
Move bbxm dispc driver to uspace.
Add arm PROCESSOR and PROCESSOR_ARCH defines.

File:

• kernel/arch/arm32/include/cp15.h (modified) (4 diffs)

kernel/arch/arm32/include/cp15.h

@@ -55 +55 @@
 
 /* Identification registers */
+enum {
+        MIDR_IMPLEMENTER_MASK = 0xff,
+        MIDR_IMPLEMENTER_SHIFT = 24,
+        MIDR_VARIANT_MASK = 0xf,
+        MIDR_VARIANT_SHIFT = 20,
+        MIDR_ARCHITECTURE_MASK = 0xf,
+        MIDR_ARCHITECTURE_SHIFT = 16,
+        MIDR_PART_NUMBER_MASK = 0xfff,
+        MIDR_PART_NUMBER_SHIFT = 4,
+        MIDR_REVISION_MASK = 0xf,
+        MIDR_REVISION_SHIFT = 0,
+};
 CONTROL_REG_GEN_READ(MIDR, c0, 0, c0, 0);
+
+enum {
+        CTR_FORMAT_MASK = 0xe0000000,
+        CTR_FORMAT_ARMv7 = 0x80000000,
+        CTR_FORMAT_ARMv6 = 0x00000000,
+        /* ARMv7 format */
+        CTR_CWG_MASK = 0xf,
+        CTR_CWG_SHIFT = 24,
+        CTR_ERG_MASK = 0xf,
+        CTR_ERG_SHIFT = 20,
+        CTR_D_MIN_LINE_MASK = 0xf,
+        CTR_D_MIN_LINE_SHIFT = 16,
+        CTR_I_MIN_LINE_MASK = 0xf,
+        CTR_I_MIN_LINE_SHIFT = 0,
+        CTR_L1I_POLICY_MASK = 0x0000c000,
+        CTR_L1I_POLICY_AIVIVT = 0x00004000,
+        CTR_L1I_POLICY_VIPT = 0x00008000,
+        CTR_L1I_POLICY_PIPT = 0x0000c000,
+        /* ARMv6 format */
+        CTR_CTYPE_MASK = 0x1e000000,
+        CTR_CTYPE_WT = 0x00000000,
+        CTR_CTYPE_WB_NL = 0x04000000,
+        CTR_CTYPE_WB_D = 0x0a000000,
+        CTR_CTYPE_WB_A = 0x0c000000, /**< ARMv5- only */
+        CTR_CTYPE_WB_B = 0x0e000000, /**< ARMv5- only */
+        CTR_CTYPE_WB_C = 0x1c000000,
+        CTR_SEP_FLAG = 1 << 24,
+        CTR_DCACHE_P_FLAG = 1 << 23,
+        CTR_DCACHE_SIZE_MASK = 0xf,
+        CTR_DCACHE_SIZE_SHIFT = 18,
+        CTR_DCACHE_ASSOC_MASK = 0x7,
+        CTR_DCACHE_ASSOC_SHIFT = 15,
+        CTR_DCACHE_M_FLAG = 1 << 14,
+        CTR_DCACHE_LEN_MASK = 0x3,
+        CTR_DCACHE_LEN_SHIFT = 0,
+        CTR_ICACHE_P_FLAG = 1 << 11,
+        CTR_ICACHE_SIZE_MASK = 0xf,
+        CTR_ICACHE_SIZE_SHIFT = 6,
+        CTR_ICACHE_ASSOC_MASK = 0x7,
+        CTR_ICACHE_ASSOC_SHIFT = 3,
+        CTR_ICACHE_M_FLAG = 1 << 2,
+        CTR_ICACHE_LEN_MASK = 0x3,
+        CTR_ICACHE_LEN_SHIFT = 0,
+};
 CONTROL_REG_GEN_READ(CTR, c0, 0, c0, 1);
 CONTROL_REG_GEN_READ(TCMR, c0, 0, c0, 2);
@@ -104 +160 @@
 CONTROL_REG_GEN_READ(ID_ISAR5, c0, 0, c2, 5);
 
+enum {
+        CCSIDR_WT_FLAG = 1 << 31,
+        CCSIDR_WB_FLAG = 1 << 30,
+        CCSIDR_RA_FLAG = 1 << 29,
+        CCSIDR_WA_FLAG = 1 << 28,
+        CCSIDR_NUMSETS_MASK = 0x7fff,
+        CCSIDR_NUMSETS_SHIFT = 13,
+        CCSIDR_ASSOC_MASK = 0x3ff,
+        CCSIDR_ASSOC_SHIFT = 3,
+        CCSIDR_LINESIZE_MASK = 0x7,
+        CCSIDR_LINESIZE_SHIFT = 0,
+};
 CONTROL_REG_GEN_READ(CCSIDR, c0, 1, c0, 0);
+
+enum {
+        CLIDR_LOUU_MASK = 0x7,
+        CLIDR_LOUU_SHIFT = 27,
+        CLIDR_LOC_MASK = 0x7,
+        CLIDR_LOC_SHIFT = 24,
+        CLIDR_LOUIS_MASK = 0x7,
+        CLIDR_LOUIS_SHIFT = 21,
+        CLIDR_NOCACHE = 0x0,
+        CLIDR_ICACHE_ONLY = 0x1,
+        CLIDR_DCACHE_ONLY = 0x2,
+        CLIDR_SEP_CACHE = 0x3,
+        CLIDR_UNI_CACHE = 0x4,
+        CLIDR_CACHE_MASK = 0x7,
+#define CLIDR_CACHE(level, val)   ((val >> (level - 1) * 3) & CLIDR_CACHE_MASK)
+};
 CONTROL_REG_GEN_READ(CLIDR, c0, 1, c0, 1);
 CONTROL_REG_GEN_READ(AIDR, c0, 1, c0, 7); /* Implementation defined or MIDR */
 
+enum {
+        CCSELR_LEVEL_MASK = 0x7,
+        CCSELR_LEVEL_SHIFT = 1,
+        CCSELR_INSTRUCTION_FLAG = 1 << 0,
+};
 CONTROL_REG_GEN_READ(CSSELR, c0, 2, c0, 0);
 CONTROL_REG_GEN_WRITE(CSSELR, c0, 2, c0, 0);
@@ -116 +205 @@
 
 /* System control registers */
+/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference
+ * Manual ARMv7-A and ARMv7-R edition, page 1687 */
+enum {
+        SCTLR_MMU_EN_FLAG            = 1 << 0,
+        SCTLR_ALIGN_CHECK_EN_FLAG    = 1 << 1,  /* Allow alignemnt check */
+        SCTLR_CACHE_EN_FLAG          = 1 << 2,
+        SCTLR_CP15_BARRIER_EN_FLAG   = 1 << 5,
+        SCTLR_B_EN_FLAG              = 1 << 7,  /* ARMv6-, big endian switch */
+        SCTLR_SWAP_EN_FLAG           = 1 << 10,
+        SCTLR_BRANCH_PREDICT_EN_FLAG = 1 << 11,
+        SCTLR_INST_CACHE_EN_FLAG     = 1 << 12,
+        SCTLR_HIGH_VECTORS_EN_FLAG   = 1 << 13,
+        SCTLR_ROUND_ROBIN_EN_FLAG    = 1 << 14,
+        SCTLR_HW_ACCESS_FLAG_EN_FLAG = 1 << 17,
+        SCTLR_WRITE_XN_EN_FLAG       = 1 << 19, /* Only if virt. supported */
+        SCTLR_USPCE_WRITE_XN_EN_FLAG = 1 << 20, /* Only if virt. supported */
+        SCTLR_FAST_IRQ_EN_FLAG       = 1 << 21, /* Disable impl. specific feat*/
+        SCTLR_UNALIGNED_EN_FLAG      = 1 << 22, /* Must be 1 on armv7 */
+        SCTLR_IRQ_VECTORS_EN_FLAG    = 1 << 24,
+        SCTLR_BIG_ENDIAN_EXC_FLAG    = 1 << 25,
+        SCTLR_NMFI_EN_FLAG           = 1 << 27,
+        SCTLR_TEX_REMAP_EN_FLAG      = 1 << 28,
+        SCTLR_ACCESS_FLAG_EN_FLAG    = 1 << 29,
+        SCTLR_THUMB_EXC_EN_FLAG      = 1 << 30,
+};
 CONTROL_REG_GEN_READ(SCTLR, c1, 0, c0, 0);
 CONTROL_REG_GEN_WRITE(SCTLR, c1, 0, c0, 0);
@@ -302 +416 @@
 CONTROL_REG_GEN_WRITE(TLBIALLNSNHS, c8, 4, c7, 4);
 
-/* c9 are reserved */
+/* c9 are performance monitoring resgisters */
+enum {
+        PMCR_IMP_MASK = 0xff,
+        PMCR_IMP_SHIFT = 24,
+        PMCR_IDCODE_MASK = 0xff,
+        PMCR_IDCODE_SHIFT = 16,
+        PMCR_EVENT_NUM_MASK = 0x1f,
+        PMCR_EVENT_NUM_SHIFT = 11,
+        PMCR_DP_FLAG = 1 << 5,
+        PMCR_X_FLAG = 1 << 4,
+        PMCR_D_FLAG = 1 << 3,
+        PMCR_C_FLAG = 1 << 2,
+        PMCR_P_FLAG = 1 << 1,
+        PMCR_E_FLAG = 1 << 0,
+};
+CONTROL_REG_GEN_READ(PMCR, c9, 0, c12, 0);
+CONTROL_REG_GEN_WRITE(PMCR, c9, 0, c12, 0);
+enum {
+        PMCNTENSET_CYCLE_COUNTER_EN_FLAG = 1 << 31,
+#define PMCNTENSET_COUNTER_EN_FLAG(c)   (1 << c)
+};
+CONTROL_REG_GEN_READ(PMCNTENSET, c9, 0, c12, 1);
+CONTROL_REG_GEN_WRITE(PMCNTENSET, c9, 0, c12, 1);
+CONTROL_REG_GEN_READ(PMCCNTR, c9, 0, c13, 0);
+CONTROL_REG_GEN_WRITE(PMCCNTR, c9, 0, c13, 0);
+
 
 /*c10 has tons of reserved too */