Changeset 005b765 in mainline for boot/arch/arm32/src/asm.S

Timestamp:

2013-01-24T22:07:06Z (13 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

03362fbd, 3acd1bb, d59c046

Parents:

6218d4b (diff), 24bead17 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge arm improvements.

Speed up boot by enabling caches early (but disable before jumping to kernel).
Add cycle counters on armv7.
Move bbxm dispc driver to uspace.
Add arm PROCESSOR and PROCESSOR_ARCH defines.

File:

• boot/arch/arm32/src/asm.S (modified) (1 diff)

boot/arch/arm32/src/asm.S

@@ -61 +61 @@
         #
 
-#if defined(MACHINE_gta02)
+        #
+        # r0 is kernel entry point
+        # r1 is pointer to the bootinfo structure
 
 #define CP15_C1_IC              12
+#define CP15_C1_BP              11
 #define CP15_C1_DC              2
-#define CP15_C7_SEG_SHIFT       5
-#define CP15_C7_SEG_SIZE        3
-#define CP15_C7_IDX_SHIFT       26
-
         # Disable I-cache and D-cache before the kernel is started.
         mrc     p15, 0, r4, c1, c0, 0
         bic     r4, r4, #(1 << CP15_C1_DC)
         bic     r4, r4, #(1 << CP15_C1_IC)
+        bic     r4, r4, #(1 << CP15_C1_BP)
         mcr     p15, 0, r4, c1, c0, 0
 
-        # Now clean D-cache to guarantee coherency between I-cache and D-cache.
+        
+        #Wait for the operations to complete
+#ifdef PROCESSOR_ARCH_armv7_a
+        dsb
+#else
+        #cp15 dsb, r4 is ignored (should be zero)
+        mcr p15, 0, r4, c7, c10, 4
+#endif
+        
+        # Clean ICache and BPredictors, r4 ignored (SBZ)
+        mcr p15, 0, r4, c7, c5, 0
+        nop
 
-        # D-cache clean and invalidate procedure.
-        # See ARM920T TRM pages 2-17, 4-17.
-
-        # Initialize segment
-        mov     r4, #0
-        # Initialize index
-1:      mov     r5, #0
-2:      orr     r6, r4, r5
-        # Clean and invalidate a single line
-        mcr     p15, 0, r6, c7, c10, 2
-        # Increment index
-        add     r5, r5, #(1 << CP15_C7_IDX_SHIFT)
-        cmp     r5, #0
-        bne     2b
-        # Increment segment
-        add     r4, #(1 << CP15_C7_SEG_SHIFT)
-        tst     r4, #(1 << (CP15_C7_SEG_SHIFT + CP15_C7_SEG_SIZE))
-        beq     1b
+        #Wait for the operations to complete
+#ifdef PROCESSOR_ARCH_armv7_a
+        isb
+        nop
+#else
+        # cp15 isb
+        mcr p15, 0, r4, c7, c5, 4
+        nop
 #endif
-
         mov pc, r0