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Version 13 (modified by Jakub Jermář, 8 years ago) (diff)

situation on Itanium

Virtual address spaces per architecture

Below are the various situations as dictated by hardware of each supported architecture and as currently used by HelenOS. The address space split is described from the kernel's point of view.


amd64

48-bit virtual address width

Starting address Size HW limitation HelenOS use
FFFF800000000000 128 TiB none kernel identity(2)
0000800000000000 16776960 TiB VA hole(1)
0000000000000000 128 TiB none uspace non-identity
  1. depends on implementation, but in practice current implementations use 48 bits
  2. physical addresses beyond the limit of physical memory are mapped non-identity

arm32

Starting address Size HW limitation HelenOS use
80000000 2 GiB none kernel identity(1)
00000000 2 GiB none uspace non-identity
  1. physical addresses beyond the limit of physical memory are mapped non-identity

ia32

Starting address Size HW limitation HelenOS use
80000000 2 GiB none kernel identity(1)
00000000 2 GiB none uspace non-identity
  1. physical addresses beyond the limit of physical memory are mapped non-identity

ia64

Itanium

(3 + 51)-bit virtual address width

Starting address Size HW limitation HelenOS use
FFFC000000000000 1 PiB VRN 7, high uspace non-identity
E00C000000000000 2046 PiB VA hole uspace non-identity
E000000000000000 1 PiB VRN 7, low uspace non-identity
DFFC000000000000 1 PiB VRN 6, high uspace non-identity
C00C000000000000 2046 PiB VA hole
C000000000000000 1 PiB VRN 6, low uspace non-identity
BFFC000000000000 1 PiB VRN 5, high uspace non-identity
A004000000000000 2046 PiB VA hole
A000000000000000 1 PiB VRN 5, low uspace non-identity
9FFC000000000000 1 PiB VRN 4, high uspace non-identity
8004000000000000 2046 PiB VA hole
8000000000000000 1 PiB VRN 4, low uspace non-identity
7FFC000000000000 1 PiB VRN 3, high uspace non-identity
600C000000000000 2046 PiB VA hole uspace non-identity
6000000000000000 1 PiB VRN 3, low uspace non-identity
5FFC000000000000 1 PiB VRN 2, high uspace non-identity
400C000000000000 2046 PiB VA hole
4000000000000000 1 PiB VRN 2, low uspace non-identity
3FFC000000000000 1 PiB VRN 1, high uspace non-identity
2004000000000000 2046 PiB VA hole
2000000000000000 1 PiB VRN 1, low uspace non-identity
1FFC000000000000 1 PiB VRN 0, high uspace non-identity
0004000000000000 2046 PiB VA hole
0000000000000000 1 PiB VRN 0, low uspace non-identity

Itanium 2

Starting address Size HW limitation HelenOS use
E000000000000000 2 EiB VRN 7 kernel identity
C000000000000000 2 EiB VRN 6 uspace non-identity
A000000000000000 2 EiB VRN 5 uspace non-identity
8000000000000000 2 EiB VRN 4 uspace non-identity
6000000000000000 2 EiB VRN 3 uspace non-identity
4000000000000000 2 EiB VRN 2 uspace non-identity
2000000000000000 2 EiB VRN 1 uspace non-identity
0000000000000000 2 EiB VRN 0 uspace non-identity

mips32

Starting address Size HW limitation HelenOS use
E0000000 512 MiB kseg3, kernel unused
C0000000 512 MiB ksseg, kernel unused
A0000000 512 MiB kseg1, kernel uncached(1) hw_map()
80000000 512 MiB kseg0, kernel identity(2) kernel identity
00000000 2 GiB kuseg, uspace uspace non-identity
  1. maps to physical 0, uncached, bypasses TLB
  2. maps to physical 0, cacheable, bypasses TLB

ppc32

Starting address Size HW limitation HelenOS use
80000000 2 GiB none kernel identity(1)
00000000 2 GiB none uspace non-identity
  1. physical addresses beyond the limit of physical memory are mapped non-identity

sparc64

UltraSPARC I, II, IIi

44-bit virtual address width

Starting address Size HW limitation HelenOS use
FFFFF80000000000 8 TiB kernel(1) kernel identity(3)
0000080000000000 16777200 TiB VA hole(2)
0000000000000000 8 TiB kernel(1) kernel identity(3)

UltraSPARC III, IIIi, IV and IV+

64-bit virtual address width

Starting address Size HW limitation HelenOS use
0000000000000000 16 EiB kernel(1) kernel identity(3)

UltraSPARC T1, T2

48-bit virtual address width

Starting address Size HW limitation HelenOS use
FFFF800000000000 128 TiB kernel(1) kernel identity(3)
0000800000000000 16776960 TiB VA hole(4), (5)
0000000000000000 128 TiB kernel(1) kernel identity(3)
  1. both kernel and uspace run in separated 64-bit address spaces
  2. no code within 4GiB reach of the VA hole on UltraSPARC I and II
  3. physical addresses beyond the limit of physical memory are identity mapped, uncachable
  4. no code within 4GiB reach of the VA hole on T1
  5. no code within 8KiB below VA hole on T2