source: mainline/kernel/arch/arm32/src/cpu/cpu.c

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(edit) @34847e2   11 years jano.vesely arm32: Up to 8 levels of cache are possible lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
(edit) @8ff767b   11 years jano.vesely armv7+: Disable Icache on IVIVT implementation lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
(edit) @8abcf4e   11 years jano.vesely armv7: Fix dcache flushing routines. lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
(edit) @c8a5c8c   11 years jano.vesely arm32: Start performance counters only if we can't use timer extensions. lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
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