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Changeset face0c04 in mainline


Ignore:
Timestamp:
2013-08-06T23:49:35Z (7 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
master
Children:
8ff767b
Parents:
bb75646
Message:

armv6+: Add pt coherency explanation.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/include/arch/mm/page_armv6.h

    rbb75646 rface0c04  
    127127
    128128
    129 //TODO: DCCMVAU should be enough but it does not work.
     129/**
     130 * For an ARMv7 implementation that does not include the Large Physical Address Extension,
     131 * and in implementations of architecture versions before ARMv7, if the translation tables
     132 * are held in Write-Back Cacheable memory, the caches must be cleaned to the point of
     133 * unification after writing to the translation tables and before the DSB instruction. This
     134 * ensures that the updated translation table are visible to a hardware translation table walk.
     135 *
     136 * Therefore, an example instruction sequence for writing a translation table entry,
     137 * covering changes to the instruction
     138 * or data mappings in a uniprocessor system is:
     139 * STR rx, [Translation table entry]
     140 * ; write new entry to the translation table
     141 * Clean cache line [Translation table entry] : This operation is not required with the
     142 * ; Multiprocessing Extensions.
     143 * DSB
     144 * ; ensures visibility of the data cleaned from the D Cache
     145 * Invalidate TLB entry by MVA (and ASID if non-global) [page address]
     146 * Invalidate BTC
     147 * DSB
     148 * ; ensure completion of the Invalidate TLB operation
     149 * ISB
     150 * ; ensure table changes visible to instruction fetch
     151 *
     152 * ARM Architecture reference chp. B3.10.1 p. B3-1375
     153 */
     154//TODO: DCCMVAU does not work.
    130155#define pt_coherence_m(pt, count) \
    131156do { \
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