Changeset e2ec980f in mainline


Ignore:
Timestamp:
2005-11-09T01:21:46Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
b183865e
Parents:
0b5ac364
Message:

ia64 work.
Big cleanup of IA-64 interrupt processing.
Merge of interrupt.c and interrupt_handler.c.
Rewrite of ivt.S and interrupt.c.
Higher level interrupt handlers are now passed a vector number and a pointer to stack structure.

ia32 work.
ia32 has ordered writes. Until it deploys weaker memory ordering model, write_barrier() can be empty statement.

Files:
1 deleted
10 edited

Legend:

Unmodified
Added
Removed

  • arch/ia32/include/barrier.h

    r0b5ac364 re2ec980f  
    5656
    5757#ifdef CONFIG_FENCES_P4
    58 #       define memory_barrier() __asm__ volatile ("mfence\n" ::: "memory")
     58#       define memory_barrier()         __asm__ volatile ("mfence\n" ::: "memory")
    5959#       define read_barrier()           __asm__ volatile ("lfence\n" ::: "memory")
    60 #       define write_barrier()          __asm__ volatile ("sfence\n" ::: "memory")
     60#       ifdef CONFIG_WEAK_MEMORY
     61#               define write_barrier()  __asm__ volatile ("sfence\n" ::: "memory")
     62#       else
     63#               define write_barrier()
     64#       endif
    6165#elif CONFIG_FENCES_P3
    6266#       define memory_barrier()         cpuid_serialization()
    6367#       define read_barrier()           cpuid_serialization()
    64 #       define write_barrier()          __asm__ volatile ("sfence\n" ::: "memory")
     68#       ifdef CONFIG_WEAK_MEMORY
     69#               define write_barrier()  __asm__ volatile ("sfence\n" ::: "memory")
     70#       else
     71#               define write_barrier()
     72#       endif
    6573#else
    6674#       define memory_barrier()         cpuid_serialization()
    6775#       define read_barrier()           cpuid_serialization()
    68 #       define write_barrier()          cpuid_serialization()
     76#       ifdef CONFIG_WEAK_MEMORY
     77#               define write_barrier()  cpuid_serialization()
     78#       else
     79#               define write_barrier()
     80#       endif
    6981#endif
    7082

  • arch/ia64/Makefile.inc

    r0b5ac364 re2ec980f  
    5555        arch/$(ARCH)/src/ivt.S \
    5656        arch/$(ARCH)/src/interrupt.c \
    57         arch/$(ARCH)/src/interrupt_handler.c \
    5857        arch/$(ARCH)/src/fmath.c \
    5958        arch/$(ARCH)/src/mm/frame.c \

  • arch/ia64/include/asm.h

    r0b5ac364 re2ec980f  
    4949}
    5050
     51/** Read IVA (Interruption Vector Address).
     52 *
     53 * @return Return location of interruption vector table.
     54 */
     55static inline __u64 iva_read(void)
     56{
     57        __u64 v;
     58       
     59        __asm__ volatile ("mov %0 = cr.iva\n" : "=r" (v));
     60       
     61        return v;
     62}
     63
     64/** Write IVA (Interruption Vector Address) register.
     65 *
     66 * @param New location of interruption vector table.
     67 */
     68static inline void iva_write(__u64 v)
     69{
     70        __asm__ volatile ("mov cr.iva = %0\n" : : "r" (v));
     71}
     72
     73
    5174/** Read IVR (External Interrupt Vector Register).
    5275 *
    … …  
    219242}
    220243
    221 #define set_shadow_register(reg,val) {__u64 v = val; __asm__  volatile("mov r15 = %0;;\n""bsw.0;;\n""mov "   #reg   " = r15;;\n""bsw.1;;\n" : : "r" (v) : "r15" ); }
    222 #define get_shadow_register(reg,val) {__u64 v ; __asm__  volatile("bsw.0;;\n" "mov r15 = r" #reg ";;\n" "bsw.1;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
    223 
    224 #define get_control_register(reg,val) {__u64 v ; __asm__  volatile("mov r15 = cr" #reg ";;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
    225 #define get_aplication_register(reg,val) {__u64 v ; __asm__  volatile("mov r15 = ar" #reg ";;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
    226 #define get_psr(val) {__u64 v ; __asm__  volatile("mov r15 = psr;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
    227 
    228244extern void cpu_halt(void);
    229245extern void cpu_sleep(void);

  • arch/ia64/include/interrupt.h

    r0b5ac364 re2ec980f  
    3030#define __ia64_INTERRUPT_H__
    3131
     32#include <arch/types.h>
     33
     34/** External interrupt vectors. */
    3235#define INTERRUPT_TIMER         0
    3336#define INTERRUPT_SPURIOUS      15
    … …  
    3538#define EOI     0               /**< The actual value doesn't matter. */
    3639
    37 extern void external_interrupt(void);
     40struct exception_regdump {
     41        __address ar_bsp;
     42        __address ar_bspstore;
     43        __u64 ar_rnat;
     44        __u64 ar_ifs;
     45        __u64 ar_pfs;
     46        __u64 ar_rsc;
     47        __address cr_ifa;
     48        __u64 cr_isr;
     49        __address cr_iipa;
     50        __u64 cr_ips;
     51        __address cr_iip;
     52        __u64 pr;
     53} __attribute__ ((packed));
     54
     55extern void *ivt;
     56
     57extern void general_exception(__u64 vector, struct exception_regdump *pstate);
     58extern void break_instruction(__u64 vector, struct exception_regdump *pstate);
     59extern void universal_handler(__u64 vector, struct exception_regdump *pstate);
     60extern void external_interrupt(__u64 vector, struct exception_regdump *pstate);
    3861
    3962#endif

  • arch/ia64/include/register.h

    r0b5ac364 re2ec980f  
    3434#define CR_IVR_MASK     0xf
    3535#define PSR_I_MASK      0x4000
     36
     37/** Application registers. */
     38#define AR_KR0          0
     39#define AR_KR1          1
     40#define AR_KR2          2
     41#define AR_KR3          3
     42#define AR_KR4          4
     43#define AR_KR5          5
     44#define AR_KR6          6
     45#define AR_KR7          7
     46/* AR 8-15 reserved */
     47#define AR_RSC          16
     48#define AR_BSP          17
     49#define AR_BSPSTORE     18
     50#define AR_RNAT         19
     51/* AR 20 reserved */
     52#define AR_FCR          21
     53/* AR 22-23 reserved */
     54#define AR_EFLAG        24
     55#define AR_CSD          25
     56#define AR_SSD          26
     57#define AR_CFLG         27
     58#define AR_FSR          28
     59#define AR_FIR          29
     60#define AR_FDR          30
     61/* AR 31 reserved */
     62#define AR_CCV          32
     63/* AR 33-35 reserved */
     64#define AR_UNAT         36
     65/* AR 37-39 reserved */
     66#define AR_FPSR         40
     67/* AR 41-43 reserved */
     68#define AR_ITC          44
     69/* AR 45-47 reserved */
     70/* AR 48-63 ignored */
     71#define AR_PFS          64
     72#define AR_LC           65
     73#define AR_EC           66
     74/* AR 67-111 reserved */
     75/* AR 112-127 ignored */
     76
     77/** Control registers. */
     78#define CR_DCR          0
     79#define CR_ITM          1
     80#define CR_IVA          2
     81/* CR3-CR7 reserved */
     82#define CR_PTA          8
     83/* CR9-CR15 reserved */
     84#define CR_IPSR         16
     85#define CR_ISR          17
     86/* CR18 reserved */
     87#define CR_IIP          19
     88#define CR_IFA          20
     89#define CR_ITIR         21
     90#define CR_IIPA         22
     91#define CR_IFS          23
     92#define CR_IIM          24
     93#define CR_IHA          25
     94/* CR26-CR63 reserved */
     95#define CR_LID          64
     96#define CR_IVR          65
     97#define CR_TPR          66
     98#define CR_EOI          67
     99#define CR_IRR0         68
     100#define CR_IRR1         69
     101#define CR_IRR2         70
     102#define CR_IRR3         71
     103#define CR_ITV          72
     104#define CR_PMV          73
     105#define CR_CMCV         74
     106/* CR75-CR79 reserved */
     107#define CR_LRR0         80
     108#define CR_LRR1         81
     109/* CR82-CR127 reserved */
    36110
    37111/** External Interrupt Vector Register */

  • arch/ia64/src/cpu/cpu.c

    r0b5ac364 re2ec980f  
    44#include <arch/types.h>
    55
    6 extern int IVT;
    7 
    8 
    9 
    10 
    116void cpu_arch_init(void)
    127{
    13 
    14 
    15 
    16     int *p=&IVT;
    17     volatile __u64 hlp,hlp2;
    18 
    19 
    20     int psr = 0x2000;
     8        int psr = 0x2000;
    219   
    22 
    2310        __asm__  volatile (
    24                 "mov cr2 = %0;;\n"
    25                 "{mov psr.l = %1;;}\n"
     11                "{mov psr.l = %0 ;;}\n"
    2612                "{srlz.i;"
    27                 "srlz.d;;}"
     13                "srlz.d ;;}"
    2814                :
    29                 : "r" (p), "r" (psr)
     15                : "r" (psr)
    3016        );
    3117
    32 
    33 
    34         /*Switch register bank of regs r16 .. r31 to 1 It is automaticly cleared on exception*/
     18        /* Switch to register bank 1. */
    3519        __asm__ volatile
    3620        (
    … …  
    3822        );             
    3923       
    40 
    4124}
    4225

  • arch/ia64/src/ia64.c

    r0b5ac364 re2ec980f  
    3030#include <arch/ski/ski.h>
    3131#include <arch/drivers/it.h>
     32#include <arch/interrupt.h>
     33#include <arch/barrier.h>
     34#include <arch/types.h>
    3235
    3336void arch_pre_mm_init(void)
    3437{
     38        /* Set Interruption Vector Address (i.e. location of interruption vector table). */
     39        iva_write((__address) &ivt);
     40        srlz_d();
     41       
    3542        ski_init_console();
    3643        it_init();

  • arch/ia64/src/interrupt.c

    r0b5ac364 re2ec980f  
    11/*
    22 * Copyright (C) 2005 Jakub Jermar
     3 * Copyright (C) 2005 Jakub Vana
    34 * All rights reserved.
    45 *
    … …  
    3738#include <arch/drivers/it.h>
    3839#include <arch.h>
     40#include <symtab.h>
     41#include <debug.h>
    3942
    40 void external_interrupt(void)
     43#define VECTORS_64_BUNDLE       20
     44#define VECTORS_16_BUNDLE       48
     45#define VECTORS_16_BUNDLE_START 0x5000
     46#define VECTOR_MAX              0x7f00
     47
     48#define BUNDLE_SIZE             16
     49
     50char *vector_names_64_bundle[VECTORS_64_BUNDLE] = {
     51        "VHPT Translation vector",
     52        "Instruction TLB vector",
     53        "Data TLB vector",
     54        "Alternate Instruction TLB vector",
     55        "Alternate Data TLB vector",
     56        "Data Nested TLB vector",
     57        "Instruction Key Miss vector",
     58        "Data Key Miss vector",
     59        "Dirty-Bit vector",
     60        "Instruction Access-Bit vector",
     61        "Data Access-Bit vector"
     62        "Break Instruction vector",
     63        "External Interrupt vector"
     64        "Reserved",
     65        "Reserved",
     66        "Reserved",
     67        "Reserved",
     68        "Reserved",
     69        "Reserved",
     70        "Reserved"
     71};
     72
     73char *vector_names_16_bundle[VECTORS_16_BUNDLE] = {
     74        "Page Not Present vector",
     75        "Key Permission vector",
     76        "Instruction Access rights vector",
     77        "Data Access Rights vector",
     78        "General Exception vector",
     79        "Disabled FP-Register vector",
     80        "NaT Consumption vector",
     81        "Speculation vector",
     82        "Reserved",
     83        "Debug vector",
     84        "Unaligned Reference vector",
     85        "Unsupported Data Reference vector",
     86        "Floating-point Fault vector",
     87        "Floating-point Trap vector",
     88        "Lower-Privilege Transfer Trap vector",
     89        "Taken Branch Trap vector",
     90        "Single STep Trap vector",
     91        "Reserved",
     92        "Reserved",
     93        "Reserved",
     94        "Reserved",
     95        "Reserved",
     96        "Reserved",
     97        "Reserved",
     98        "Reserved",
     99        "IA-32 Exception vector",
     100        "IA-32 Intercept vector",
     101        "IA-32 Interrupt vector",
     102        "Reserved",
     103        "Reserved",
     104        "Reserved"
     105};
     106
     107static char *vector_to_string(__u16 vector);
     108static void dump_stack(struct exception_regdump *pstate);
     109
     110char *vector_to_string(__u16 vector)
     111{
     112        ASSERT(vector <= VECTOR_MAX);
     113       
     114        if (vector >= VECTORS_16_BUNDLE_START)
     115                return vector_names_16_bundle[(vector-VECTORS_16_BUNDLE_START)/(16*BUNDLE_SIZE)];
     116        else
     117                return vector_names_64_bundle[vector/(64*BUNDLE_SIZE)];
     118}
     119
     120void dump_stack(struct exception_regdump *pstate)
     121{
     122        char *ifa, *iipa, *iip;
     123
     124        ifa = get_symtab_entry(pstate->cr_ifa);
     125        iipa = get_symtab_entry(pstate->cr_iipa);
     126        iip = get_symtab_entry(pstate->cr_iip);
     127
     128        putchar('\n');
     129        printf("ar.bsp=%P\tar.bspstore=%P\n", pstate->ar_bsp, pstate->ar_bspstore);
     130        printf("ar.rnat=%Q\tar.rsc=%Q\n", pstate->ar_rnat, pstate->ar_rsc);
     131        printf("ar.ifs=%Q\tar.pfs=%Q\n", pstate->ar_ifs, pstate->ar_pfs);
     132        printf("cr.isr=%Q\tcr.ips=%Q\t\n", pstate->cr_isr, pstate->cr_ips);
     133       
     134        printf("cr.iip=%Q (%s)\n", pstate->cr_iip, iip ? iip : "?");
     135        printf("cr.iipa=%Q (%s)\n", pstate->cr_iipa, iipa ? iipa : "?");
     136        printf("cr.ifa=%Q (%s)\n", pstate->cr_ifa, ifa ? ifa : "?");
     137}
     138
     139void general_exception(__u64 vector, struct exception_regdump *pstate)
     140{
     141        dump_stack(pstate);
     142        panic("General Exception\n");
     143}
     144
     145void break_instruction(__u64 vector, struct exception_regdump *pstate)
     146{
     147        dump_stack(pstate);
     148        panic("Break Instruction\n");
     149}
     150
     151void universal_handler(__u64 vector, struct exception_regdump *pstate)
     152{
     153        dump_stack(pstate);
     154        panic("Interruption: %W (%s)\n", (__u16) vector, vector_to_string(vector));
     155}
     156
     157void external_interrupt(__u64 vector, struct exception_regdump *pstate)
    41158{
    42159        cr_ivr_t ivr;

  • arch/ia64/src/ivt.S

    r0b5ac364 re2ec980f  
    5151 * @param handler Interrupt handler address.
    5252 */
    53 .macro HEAVYWEIGHT_HANDLER offs handler
    54     .org IVT + \offs
    55 
     53.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
     54    .org ivt + \offs
     55        mov r24 = \offs
     56        movl r25 = \handler ;;
     57        mov ar.k0 = r24
     58        mov ar.k1 = r25
     59        br heavyweight_handler
     60.endm
     61
     62.global heavyweight_handler
     63heavyweight_handler:
    5664    /* 1. copy interrupt registers into bank 0 */
    5765        mov r24 = cr.iip
    … …  
    6876        /* assume kernel stack */
    6977       
    70     /* 4. save registers in bank 0 into memory stack */
    7178        add r31 = -8, r12 ;;
    72         add r12 = -STACK_FRAME_SIZE, r12 ;;
    73        
     79        add r12 = -STACK_FRAME_SIZE, r12
     80
     81    /* 4. save registers in bank 0 into memory stack */
    7482        st8 [r31] = r29, -8 ;;  /* save predicate registers */
    7583
    … …  
    7886        st8 [r31] = r26, -8 ;;  /* save cr.iipa */
    7987        st8 [r31] = r27, -8 ;;  /* save cr.isr */
    80         st8 [r31] = r28, -8 ;;  /* save cr.ifa */               
     88        st8 [r31] = r28, -8     /* save cr.ifa */               
    8189
    8290    /* 5. RSE switch from interrupted context */
    83         .auto
    8491        mov r24 = ar.rsc
    8592        mov r25 = ar.pfs
    … …  
    8794        mov r26 = cr.ifs
    8895       
    89         st8 [r31] = r24, -8     /* save ar.rsc */
    90         st8 [r31] = r25, -8     /* save ar.pfs */
     96        st8 [r31] = r24, -8;;   /* save ar.rsc */
     97        st8 [r31] = r25, -8;;   /* save ar.pfs */
    9198        st8 [r31] = r26, -8     /* save ar.ifs */
    9299       
    93         and r30 = ~3, r24
    94         mov ar.rsc = r30        /* place RSE in enforced lazy mode */
     100        and r30 = ~3, r24 ;;
     101        mov ar.rsc = r30 ;;     /* place RSE in enforced lazy mode */
    95102       
    96103        mov r27 = ar.rnat
    97         mov r28 = ar.bspstore
     104        mov r28 = ar.bspstore ;;
    98105       
    99106        /* assume kernel backing store */
    100         mov ar.bspstore = r28
     107        mov ar.bspstore = r28 ;;
    101108       
    102109        mov r29 = ar.bsp
    103110       
    104         st8 [r31] = r27, -8     /* save ar.rnat */
    105         st8 [r31] = r28, -8     /* save ar.bspstore */
     111        st8 [r31] = r27, -8 ;;  /* save ar.rnat */
     112        st8 [r31] = r28, -8 ;;  /* save ar.bspstore */
    106113        st8 [r31] = r29, -8     /* save ar.bsp */
    107114       
    108115        mov ar.rsc = r24        /* restore RSE's setting */
    109         .explicit
    110        
    111     /* the rest of the save-handler can be kept outside IVT */
    112 
    113         movl r24 = \handler
    114         mov r25 = b0
     116       
     117    /* steps 6 - 15 are done by heavyweight_handler_inner() */
     118        mov r24 = b0            /* save b0 belonging to interrupted context */
     119        mov r26 = ar.k0
     120        mov r25 = ar.k1
    115121        br.call.sptk.many rp = heavyweight_handler_inner
    116 0:      mov b0 = r25   
    117 
    118         br heavyweight_handler_finalize
    119 .endm
     1220:      mov b0 = r24            /* restore b0 belonging to the interrupted context */
     123
     124    /* 16. RSE switch to interrupted context */
     125        cover                   /* allocate zerro size frame (step 1 (from Intel Docs)) */
     126
     127        add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;
     128
     129        mov r28 = ar.bspstore           /* calculate loadrs (step 2) */
     130        ld8 r29 = [r31], +8 ;;          /* load ar.bsp */
     131        sub r27 = r29 , r28 ;;
     132        shl r27 = r27, 16
     133
     134        mov r24 = ar.rsc ;;
     135        and r30 = ~3, r24 ;;
     136        or  r24 = r30 , r27 ;;     
     137        mov ar.rsc = r24 ;;             /* place RSE in enforced lazy mode */
     138
     139        loadrs                          /* (step 3) */
     140
     141        ld8 r28 = [r31], +8 ;;          /* load ar.bspstore */
     142        ld8 r27 = [r31], +8 ;;          /* load ar.rnat */
     143        ld8 r26 = [r31], +8 ;;          /* load cr.ifs */
     144        ld8 r25 = [r31], +8 ;;          /* load ar.pfs */
     145        ld8 r24 = [r31], +8 ;;          /* load ar.rsc */
     146
     147        mov ar.bspstore = r28 ;;        /* (step 4) */
     148        mov ar.rnat = r27               /* (step 5) */
     149
     150        mov ar.pfs = r25                /* (step 6) */
     151        mov cr.ifs = r26       
     152
     153        mov ar.rsc = r24                /* (step 7) */
     154
     155    /* 17. restore interruption state from memory stack */
     156        ld8 r28 = [r31], +8 ;;  /* load cr.ifa */               
     157        ld8 r27 = [r31], +8 ;;  /* load cr.isr */
     158        ld8 r26 = [r31], +8 ;;  /* load cr.iipa */
     159        ld8 r25 = [r31], +8 ;;  /* load cr.ipsr */
     160        ld8 r24 = [r31], +8 ;;  /* load cr.iip */
     161
     162        mov cr.iip = r24
     163        mov cr.ipsr = r25
     164        mov cr.iipa = r26
     165        mov cr.isr = r27
     166        mov cr.ifa = r28
     167
     168    /* 18. restore predicate registers from memory stack */
     169        ld8 r29 = [r31] , -8 ;; /* load predicate registers */
     170        mov pr = r29
     171       
     172    /* 19. return from interruption */
     173        add r12 = STACK_FRAME_SIZE, r12
     174        rfi ;;
    120175
    121176.global heavyweight_handler_inner
    … …  
    125180         * will be preserved in stacked registers and backing store.
    126181         */
    127         alloc loc0 = ar.pfs, 0, 46, 0, 0 ;;
    128        
    129         /* copy handler address (r24 from bank 0 will be invisible soon) */
    130         mov loc1 = r24
     182        alloc loc0 = ar.pfs, 0, 47, 2, 0 ;;
     183       
     184        /* bank 0 is going to be shadowed, copy essential data from there */
     185        mov loc1 = r24  /* b0 belonging to interrupted context */
     186        mov loc2 = r25
     187        mov out0 = r26
     188       
     189        add out1 = STACK_SCRATCH_AREA_SIZE, r12
    131190
    132191    /* 6. switch to bank 1 and reenable PSR.ic */
    … …  
    136195       
    137196    /* 7. preserve branch and application registers */
    138         mov loc2 = ar.unat
    139         mov loc3 = ar.lc
    140         mov loc4 = ar.ec
    141         mov loc5 = ar.ccv
    142         mov loc6 = ar.csd
    143         mov loc7 = ar.ssd
    144        
    145         mov loc8 = b0
    146         mov loc9 = b1
    147         mov loc10 = b2
    148         mov loc11 = b3
    149         mov loc12 = b4
    150         mov loc13 = b5
    151         mov loc14 = b6
    152         mov loc15 = b7
     197        mov loc3 = ar.unat
     198        mov loc4 = ar.lc
     199        mov loc5 = ar.ec
     200        mov loc6 = ar.ccv
     201        mov loc7 = ar.csd
     202        mov loc8 = ar.ssd
     203       
     204        mov loc9 = b0
     205        mov loc10 = b1
     206        mov loc11 = b2
     207        mov loc12 = b3
     208        mov loc13 = b4
     209        mov loc14 = b5
     210        mov loc15 = b6
     211        mov loc16 = b7
    153212       
    154213    /* 8. preserve general and floating-point registers */
    155214        /* TODO: save floating-point context */
    156         mov loc16 = r1
    157         mov loc17 = r2
    158         mov loc18 = r3
    159         mov loc19 = r4
    160         mov loc20 = r5
    161         mov loc21 = r6
    162         mov loc22 = r7
    163         mov loc23 = r8
    164         mov loc24 = r9
    165         mov loc25 = r10
    166         mov loc26 = r11
     215        mov loc17 = r1
     216        mov loc18 = r2
     217        mov loc19 = r3
     218        mov loc20 = r4
     219        mov loc21 = r5
     220        mov loc22 = r6
     221        mov loc23 = r7
     222        mov loc24 = r8
     223        mov loc25 = r9
     224        mov loc26 = r10
     225        mov loc27 = r11
    167226        /* skip r12 (stack pointer) */
    168         mov loc27 = r13
    169         mov loc28 = r14
    170         mov loc29 = r15
    171         mov loc30 = r16
    172         mov loc31 = r17
    173         mov loc32 = r18
    174         mov loc33 = r19
    175         mov loc34 = r20
    176         mov loc35 = r21
    177         mov loc36 = r22
    178         mov loc37 = r23
    179         mov loc38 = r24
    180         mov loc39 = r25
    181         mov loc40 = r26
    182         mov loc41 = r27
    183         mov loc42 = r28
    184         mov loc43 = r29
    185         mov loc44 = r30
    186         mov loc45 = r31
     227        mov loc28 = r13
     228        mov loc29 = r14
     229        mov loc30 = r15
     230        mov loc31 = r16
     231        mov loc32 = r17
     232        mov loc33 = r18
     233        mov loc34 = r19
     234        mov loc35 = r20
     235        mov loc36 = r21
     236        mov loc37 = r22
     237        mov loc38 = r23
     238        mov loc39 = r24
     239        mov loc40 = r25
     240        mov loc41 = r26
     241        mov loc42 = r27
     242        mov loc43 = r28
     243        mov loc44 = r29
     244        mov loc45 = r30
     245        mov loc46 = r31
    187246   
    188247    /* 9. skipped (will not enable interrupts) */
    189248
    190249    /* 10. call handler */
    191         mov b1 = loc1
     250        mov b1 = loc2
    192251        br.call.sptk.many b0 = b1
    193252
    … …  
    199258    /* 13. restore general and floating-point registers */
    200259        /* TODO: restore floating-point context */
    201         mov r1 = loc16
    202         mov r2 = loc17
    203         mov r3 = loc18
    204         mov r4 = loc19
    205         mov r5 = loc20
    206         mov r6 = loc21
    207         mov r7 = loc22
    208         mov r8 = loc23
    209         mov r9 = loc24
    210         mov r10 = loc25
    211         mov r11 = loc26
     260        mov r1 = loc17
     261        mov r2 = loc18
     262        mov r3 = loc19
     263        mov r4 = loc20
     264        mov r5 = loc21
     265        mov r6 = loc22
     266        mov r7 = loc23
     267        mov r8 = loc24
     268        mov r9 = loc25
     269        mov r10 = loc26
     270        mov r11 = loc27
    212271        /* skip r12 (stack pointer) */
    213         mov r13 = loc27
    214         mov r14 = loc28
    215         mov r15 = loc29
    216         mov r16 = loc30
    217         mov r17 = loc31
    218         mov r18 = loc32
    219         mov r19 = loc33
    220         mov r20 = loc34
    221         mov r21 = loc35
    222         mov r22 = loc36
    223         mov r23 = loc37
    224         mov r24 = loc38
    225         mov r25 = loc39
    226         mov r26 = loc40
    227         mov r27 = loc41
    228         mov r28 = loc42
    229         mov r29 = loc43
    230         mov r30 = loc44
    231         mov r31 = loc45
     272        mov r13 = loc28
     273        mov r14 = loc29
     274        mov r15 = loc30
     275        mov r16 = loc31
     276        mov r17 = loc32
     277        mov r18 = loc33
     278        mov r19 = loc34
     279        mov r20 = loc35
     280        mov r21 = loc36
     281        mov r22 = loc37
     282        mov r23 = loc38
     283        mov r24 = loc39
     284        mov r25 = loc40
     285        mov r26 = loc41
     286        mov r27 = loc42
     287        mov r28 = loc43
     288        mov r29 = loc44
     289        mov r30 = loc45
     290        mov r31 = loc46
    232291       
    233292    /* 14. restore branch and application registers */
    234         mov ar.unat = loc2
    235         mov ar.lc = loc3
    236         mov ar.ec = loc4
    237         mov ar.ccv = loc5
    238         mov ar.csd = loc6
    239         mov ar.ssd = loc7
    240        
    241         mov b0 = loc8
    242         mov b1 = loc9
    243         mov b2 = loc10
    244         mov b3 = loc11
    245         mov b4 = loc12
    246         mov b5 = loc13
    247         mov b6 = loc14
    248         mov b7 = loc15
     293        mov ar.unat = loc3
     294        mov ar.lc = loc4
     295        mov ar.ec = loc5
     296        mov ar.ccv = loc6
     297        mov ar.csd = loc7
     298        mov ar.ssd = loc8
     299       
     300        mov b0 = loc9
     301        mov b1 = loc10
     302        mov b2 = loc11
     303        mov b3 = loc12
     304        mov b4 = loc13
     305        mov b5 = loc14
     306        mov b6 = loc15
     307        mov b7 = loc16
    249308       
    250309    /* 15. disable PSR.ic and switch to bank 0 */
    … …  
    253312        srlz.d
    254313
     314        mov r24 = loc1
    255315        mov ar.pfs = loc0
    256         br.ret.sptk.many rp
    257 
    258 .global heavyweight_handler_finalize
    259 heavyweight_handler_finalize:
    260     /* 16. RSE switch to interrupted context */
    261         .auto
    262         cover                   /* allocate zerro size frame (step 1 (from Intel Docs)) */
    263 
    264         add r31 = STACK_SCRATCH_AREA_SIZE, r12
    265 
    266         mov r28 = ar.bspstore   /* calculate loadrs (step 2) */
    267         ld8 r29 = [r31], +8     /* load ar.bsp */
    268         sub r27 = r29 , r28
    269         shl r27 = r27, 16
    270 
    271         mov r24 = ar.rsc
    272         and r30 = ~3, r24
    273         or  r24 = r30 , r27     
    274         mov ar.rsc = r24        /* place RSE in enforced lazy mode */
    275 
    276         loadrs                  /* (step 3) */
    277 
    278         ld8 r28 = [r31], +8     /* load ar.bspstore */
    279         ld8 r27 = [r31], +8     /* load ar.rnat */
    280         ld8 r26 = [r31], +8     /* load cr.ifs */
    281         ld8 r25 = [r31], +8     /* load ar.pfs */
    282         ld8 r24 = [r31], +8     /* load ar.rsc */
    283 
    284         mov ar.bspstore = r28   /* (step 4) */
    285         mov ar.rnat = r27       /* (step 5) */
    286 
    287         mov ar.pfs = r25        /* (step 6) */
    288         mov cr.ifs = r26       
    289 
    290         mov ar.rsc = r24        /* (step 7) */
    291         .explicit       
    292 
    293     /* 17. restore interruption state from memory stack */
    294         ld8 r28 = [r31], +8 ;;  /* load cr.ifa */               
    295         ld8 r27 = [r31], +8 ;;  /* load cr.isr */
    296         ld8 r26 = [r31], +8 ;;  /* load cr.iipa */
    297         ld8 r25 = [r31], +8 ;;  /* load cr.ipsr */
    298         ld8 r24 = [r31], +8 ;;  /* load cr.iip */
    299 
    300         mov cr.iip = r24
    301         mov cr.ipsr = r25
    302         mov cr.iipa = r26
    303         mov cr.isr = r27
    304         mov cr.ifa = r28
    305 
    306     /* 18. restore predicate registers from memory stack */
    307         ld8 r29 = [r31] , -8 ;; /* load predicate registers */
    308         mov pr = r29
    309        
    310     /* 19. return from interruption */
    311         add r12 = STACK_FRAME_SIZE, r12
    312         rfi ;;
    313 
    314 dump_gregs:
    315 mov r16 = REG_DUMP;;
    316 st8 [r16] = r0;;
    317 add r16 = 8,r16 ;;
    318 st8 [r16] = r1;;
    319 add r16 = 8,r16 ;;
    320 st8 [r16] = r2;;
    321 add r16 = 8,r16 ;;
    322 st8 [r16] = r3;;
    323 add r16 = 8,r16 ;;
    324 st8 [r16] = r4;;
    325 add r16 = 8,r16 ;;
    326 st8 [r16] = r5;;
    327 add r16 = 8,r16 ;;
    328 st8 [r16] = r6;;
    329 add r16 = 8,r16 ;;
    330 st8 [r16] = r7;;
    331 add r16 = 8,r16 ;;
    332 st8 [r16] = r8;;
    333 add r16 = 8,r16 ;;
    334 st8 [r16] = r9;;
    335 add r16 = 8,r16 ;;
    336 st8 [r16] = r10;;
    337 add r16 = 8,r16 ;;
    338 st8 [r16] = r11;;
    339 add r16 = 8,r16 ;;
    340 st8 [r16] = r12;;
    341 add r16 = 8,r16 ;;
    342 st8 [r16] = r13;;
    343 add r16 = 8,r16 ;;
    344 st8 [r16] = r14;;
    345 add r16 = 8,r16 ;;
    346 st8 [r16] = r15;;
    347 add r16 = 8,r16 ;;
    348 
    349 bsw.1;;
    350 mov r15 = r16;;
    351 bsw.0;;
    352 st8 [r16] = r15;;
    353 add r16 = 8,r16 ;;
    354 bsw.1;;
    355 mov r15 = r17;;
    356 bsw.0;;
    357 st8 [r16] = r15;;
    358 add r16 = 8,r16 ;;
    359 bsw.1;;
    360 mov r15 = r18;;
    361 bsw.0;;
    362 st8 [r16] = r15;;
    363 add r16 = 8,r16 ;;
    364 bsw.1;;
    365 mov r15 = r19;;
    366 bsw.0;;
    367 st8 [r16] = r15;;
    368 add r16 = 8,r16 ;;
    369 bsw.1;;
    370 mov r15 = r20;;
    371 bsw.0;;
    372 st8 [r16] = r15;;
    373 add r16 = 8,r16 ;;
    374 bsw.1;;
    375 mov r15 = r21;;
    376 bsw.0;;
    377 st8 [r16] = r15;;
    378 add r16 = 8,r16 ;;
    379 bsw.1;;
    380 mov r15 = r22;;
    381 bsw.0;;
    382 st8 [r16] = r15;;
    383 add r16 = 8,r16 ;;
    384 bsw.1;;
    385 mov r15 = r23;;
    386 bsw.0;;
    387 st8 [r16] = r15;;
    388 add r16 = 8,r16 ;;
    389 bsw.1;;
    390 mov r15 = r24;;
    391 bsw.0;;
    392 st8 [r16] = r15;;
    393 add r16 = 8,r16 ;;
    394 bsw.1;;
    395 mov r15 = r25;;
    396 bsw.0;;
    397 st8 [r16] = r15;;
    398 add r16 = 8,r16 ;;
    399 bsw.1;;
    400 mov r15 = r26;;
    401 bsw.0;;
    402 st8 [r16] = r15;;
    403 add r16 = 8,r16 ;;
    404 bsw.1;;
    405 mov r15 = r27;;
    406 bsw.0;;
    407 st8 [r16] = r15;;
    408 add r16 = 8,r16 ;;
    409 bsw.1;;
    410 mov r15 = r28;;
    411 bsw.0;;
    412 st8 [r16] = r15;;
    413 add r16 = 8,r16 ;;
    414 bsw.1;;
    415 mov r15 = r29;;
    416 bsw.0;;
    417 st8 [r16] = r15;;
    418 add r16 = 8,r16 ;;
    419 bsw.1;;
    420 mov r15 = r30;;
    421 bsw.0;;
    422 st8 [r16] = r15;;
    423 add r16 = 8,r16 ;;
    424 bsw.1;;
    425 mov r15 = r31;;
    426 bsw.0;;
    427 st8 [r16] = r15;;
    428 add r16 = 8,r16 ;;
    429 
    430 
    431 st8 [r16] = r32;;
    432 add r16 = 8,r16 ;;
    433 st8 [r16] = r33;;
    434 add r16 = 8,r16 ;;
    435 st8 [r16] = r34;;
    436 add r16 = 8,r16 ;;
    437 st8 [r16] = r35;;
    438 add r16 = 8,r16 ;;
    439 st8 [r16] = r36;;
    440 add r16 = 8,r16 ;;
    441 st8 [r16] = r37;;
    442 add r16 = 8,r16 ;;
    443 st8 [r16] = r38;;
    444 add r16 = 8,r16 ;;
    445 st8 [r16] = r39;;
    446 add r16 = 8,r16 ;;
    447 st8 [r16] = r40;;
    448 add r16 = 8,r16 ;;
    449 st8 [r16] = r41;;
    450 add r16 = 8,r16 ;;
    451 st8 [r16] = r42;;
    452 add r16 = 8,r16 ;;
    453 st8 [r16] = r43;;
    454 add r16 = 8,r16 ;;
    455 st8 [r16] = r44;;
    456 add r16 = 8,r16 ;;
    457 st8 [r16] = r45;;
    458 add r16 = 8,r16 ;;
    459 st8 [r16] = r46;;
    460 add r16 = 8,r16 ;;
    461 st8 [r16] = r47;;
    462 add r16 = 8,r16 ;;
    463 st8 [r16] = r48;;
    464 add r16 = 8,r16 ;;
    465 st8 [r16] = r49;;
    466 add r16 = 8,r16 ;;
    467 st8 [r16] = r50;;
    468 add r16 = 8,r16 ;;
    469 st8 [r16] = r51;;
    470 add r16 = 8,r16 ;;
    471 st8 [r16] = r52;;
    472 add r16 = 8,r16 ;;
    473 st8 [r16] = r53;;
    474 add r16 = 8,r16 ;;
    475 st8 [r16] = r54;;
    476 add r16 = 8,r16 ;;
    477 st8 [r16] = r55;;
    478 add r16 = 8,r16 ;;
    479 st8 [r16] = r56;;
    480 add r16 = 8,r16 ;;
    481 st8 [r16] = r57;;
    482 add r16 = 8,r16 ;;
    483 st8 [r16] = r58;;
    484 add r16 = 8,r16 ;;
    485 st8 [r16] = r59;;
    486 add r16 = 8,r16 ;;
    487 st8 [r16] = r60;;
    488 add r16 = 8,r16 ;;
    489 st8 [r16] = r61;;
    490 add r16 = 8,r16 ;;
    491 st8 [r16] = r62;;
    492 add r16 = 8,r16 ;;
    493 st8 [r16] = r63;;
    494 add r16 = 8,r16 ;;
    495 
    496 
    497 
    498 st8 [r16] = r64;;
    499 add r16 = 8,r16 ;;
    500 st8 [r16] = r65;;
    501 add r16 = 8,r16 ;;
    502 st8 [r16] = r66;;
    503 add r16 = 8,r16 ;;
    504 st8 [r16] = r67;;
    505 add r16 = 8,r16 ;;
    506 st8 [r16] = r68;;
    507 add r16 = 8,r16 ;;
    508 st8 [r16] = r69;;
    509 add r16 = 8,r16 ;;
    510 st8 [r16] = r70;;
    511 add r16 = 8,r16 ;;
    512 st8 [r16] = r71;;
    513 add r16 = 8,r16 ;;
    514 st8 [r16] = r72;;
    515 add r16 = 8,r16 ;;
    516 st8 [r16] = r73;;
    517 add r16 = 8,r16 ;;
    518 st8 [r16] = r74;;
    519 add r16 = 8,r16 ;;
    520 st8 [r16] = r75;;
    521 add r16 = 8,r16 ;;
    522 st8 [r16] = r76;;
    523 add r16 = 8,r16 ;;
    524 st8 [r16] = r77;;
    525 add r16 = 8,r16 ;;
    526 st8 [r16] = r78;;
    527 add r16 = 8,r16 ;;
    528 st8 [r16] = r79;;
    529 add r16 = 8,r16 ;;
    530 st8 [r16] = r80;;
    531 add r16 = 8,r16 ;;
    532 st8 [r16] = r81;;
    533 add r16 = 8,r16 ;;
    534 st8 [r16] = r82;;
    535 add r16 = 8,r16 ;;
    536 st8 [r16] = r83;;
    537 add r16 = 8,r16 ;;
    538 st8 [r16] = r84;;
    539 add r16 = 8,r16 ;;
    540 st8 [r16] = r85;;
    541 add r16 = 8,r16 ;;
    542 st8 [r16] = r86;;
    543 add r16 = 8,r16 ;;
    544 st8 [r16] = r87;;
    545 add r16 = 8,r16 ;;
    546 st8 [r16] = r88;;
    547 add r16 = 8,r16 ;;
    548 st8 [r16] = r89;;
    549 add r16 = 8,r16 ;;
    550 st8 [r16] = r90;;
    551 add r16 = 8,r16 ;;
    552 st8 [r16] = r91;;
    553 add r16 = 8,r16 ;;
    554 st8 [r16] = r92;;
    555 add r16 = 8,r16 ;;
    556 st8 [r16] = r93;;
    557 add r16 = 8,r16 ;;
    558 st8 [r16] = r94;;
    559 add r16 = 8,r16 ;;
    560 st8 [r16] = r95;;
    561 add r16 = 8,r16 ;;
    562 
    563 
    564 
    565 st8 [r16] = r96;;
    566 add r16 = 8,r16 ;;
    567 st8 [r16] = r97;;
    568 add r16 = 8,r16 ;;
    569 st8 [r16] = r98;;
    570 add r16 = 8,r16 ;;
    571 st8 [r16] = r99;;
    572 add r16 = 8,r16 ;;
    573 st8 [r16] = r100;;
    574 add r16 = 8,r16 ;;
    575 st8 [r16] = r101;;
    576 add r16 = 8,r16 ;;
    577 st8 [r16] = r102;;
    578 add r16 = 8,r16 ;;
    579 st8 [r16] = r103;;
    580 add r16 = 8,r16 ;;
    581 st8 [r16] = r104;;
    582 add r16 = 8,r16 ;;
    583 st8 [r16] = r105;;
    584 add r16 = 8,r16 ;;
    585 st8 [r16] = r106;;
    586 add r16 = 8,r16 ;;
    587 st8 [r16] = r107;;
    588 add r16 = 8,r16 ;;
    589 st8 [r16] = r108;;
    590 add r16 = 8,r16 ;;
    591 st8 [r16] = r109;;
    592 add r16 = 8,r16 ;;
    593 st8 [r16] = r110;;
    594 add r16 = 8,r16 ;;
    595 st8 [r16] = r111;;
    596 add r16 = 8,r16 ;;
    597 st8 [r16] = r112;;
    598 add r16 = 8,r16 ;;
    599 st8 [r16] = r113;;
    600 add r16 = 8,r16 ;;
    601 st8 [r16] = r114;;
    602 add r16 = 8,r16 ;;
    603 st8 [r16] = r115;;
    604 add r16 = 8,r16 ;;
    605 st8 [r16] = r116;;
    606 add r16 = 8,r16 ;;
    607 st8 [r16] = r117;;
    608 add r16 = 8,r16 ;;
    609 st8 [r16] = r118;;
    610 add r16 = 8,r16 ;;
    611 st8 [r16] = r119;;
    612 add r16 = 8,r16 ;;
    613 st8 [r16] = r120;;
    614 add r16 = 8,r16 ;;
    615 st8 [r16] = r121;;
    616 add r16 = 8,r16 ;;
    617 st8 [r16] = r122;;
    618 add r16 = 8,r16 ;;
    619 st8 [r16] = r123;;
    620 add r16 = 8,r16 ;;
    621 st8 [r16] = r124;;
    622 add r16 = 8,r16 ;;
    623 st8 [r16] = r125;;
    624 add r16 = 8,r16 ;;
    625 st8 [r16] = r126;;
    626 add r16 = 8,r16 ;;
    627 st8 [r16] = r127;;
    628 add r16 = 8,r16 ;;
    629 
    630 
    631 
    632 br.ret.sptk.many b0;;
    633 
    634 
    635 
    636 
    637 
    638 .macro Handler o h
    639 .org IVT + \o
    640 br \h;;
    641 .endm
    642 
    643 .macro Handler2 o
    644 .org IVT + \o
    645 br.call.sptk.many b0 = dump_gregs;;
    646 mov r16 = \o ;;
    647 bsw.1;;
    648 br universal_handler;;
    649 .endm
    650 
    651 
    652 
    653 .global IVT
     316        br.ret.sptk.many b0
     317
     318.global ivt
    654319.align 32768
    655 IVT:
    656 
    657 
    658 Handler2 0x0000
    659 Handler2 0x0400
    660 Handler2 0x0800
    661 Handler2 0x0c00
    662 Handler2 0x1000
    663 Handler2 0x1400
    664 Handler2 0x1800
    665 Handler2 0x1c00
    666 Handler2 0x2000
    667 Handler2 0x2400
    668 Handler2 0x2800
    669 Handler 0x2c00 break_instruction
    670 HEAVYWEIGHT_HANDLER 0x3000 external_interrupt   /* For external interrupt, heavyweight handler is used. */
    671 Handler2 0x3400
    672 Handler2 0x3800
    673 Handler2 0x3c00
    674 Handler2 0x4000
    675 Handler2 0x4400
    676 Handler2 0x4800
    677 Handler2 0x4c00
    678 
    679 Handler2 0x5000
    680 Handler2 0x5100
    681 Handler2 0x5200
    682 Handler2 0x5300
    683 #Handler 0x5400 general_exception
    684 Handler2 0x5400
    685 Handler2 0x5500
    686 Handler2 0x5600
    687 Handler2 0x5700
    688 Handler2 0x5800
    689 Handler2 0x5900
    690 Handler2 0x5a00
    691 Handler2 0x5b00
    692 Handler2 0x5c00
    693 Handler2 0x5d00
    694 Handler2 0x5e00
    695 Handler2 0x5f00
    696 
    697 Handler2 0x6000
    698 Handler2 0x6100
    699 Handler2 0x6200
    700 Handler2 0x6300
    701 Handler2 0x6400
    702 Handler2 0x6500
    703 Handler2 0x6600
    704 Handler2 0x6700
    705 Handler2 0x6800
    706 Handler2 0x6900
    707 Handler2 0x6a00
    708 Handler2 0x6b00
    709 Handler2 0x6c00
    710 Handler2 0x6d00
    711 Handler2 0x6e00
    712 Handler2 0x6f00
    713 
    714 Handler2 0x7000
    715 Handler2 0x7100
    716 Handler2 0x7200
    717 Handler2 0x7300
    718 Handler2 0x7400
    719 Handler2 0x7500
    720 Handler2 0x7600
    721 Handler2 0x7700
    722 Handler2 0x7800
    723 Handler2 0x7900
    724 Handler2 0x7a00
    725 Handler2 0x7b00
    726 Handler2 0x7c00
    727 Handler2 0x7d00
    728 Handler2 0x7e00
    729 Handler2 0x7f00
    730 
    731 
    732 
    733 
    734 
    735 
    736 
    737 
    738 .align 32768
    739 .global REG_DUMP
    740 
    741 REG_DUMP:
    742 .space 128*8
    743 
     320ivt:
     321        HEAVYWEIGHT_HANDLER 0x0000
     322        HEAVYWEIGHT_HANDLER 0x0400
     323        HEAVYWEIGHT_HANDLER 0x0800
     324        HEAVYWEIGHT_HANDLER 0x0c00
     325        HEAVYWEIGHT_HANDLER 0x1000
     326        HEAVYWEIGHT_HANDLER 0x1400
     327        HEAVYWEIGHT_HANDLER 0x1800
     328        HEAVYWEIGHT_HANDLER 0x1c00
     329        HEAVYWEIGHT_HANDLER 0x2000
     330        HEAVYWEIGHT_HANDLER 0x2400
     331        HEAVYWEIGHT_HANDLER 0x2800
     332        HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
     333        HEAVYWEIGHT_HANDLER 0x3000 external_interrupt   /* For external interrupt, heavyweight handler is used. */
     334        HEAVYWEIGHT_HANDLER 0x3400
     335        HEAVYWEIGHT_HANDLER 0x3800
     336        HEAVYWEIGHT_HANDLER 0x3c00
     337        HEAVYWEIGHT_HANDLER 0x4000
     338        HEAVYWEIGHT_HANDLER 0x4400
     339        HEAVYWEIGHT_HANDLER 0x4800
     340        HEAVYWEIGHT_HANDLER 0x4c00
     341
     342        HEAVYWEIGHT_HANDLER 0x5000
     343        HEAVYWEIGHT_HANDLER 0x5100
     344        HEAVYWEIGHT_HANDLER 0x5200
     345        HEAVYWEIGHT_HANDLER 0x5300
     346        HEAVYWEIGHT_HANDLER 0x5400 general_exception
     347        HEAVYWEIGHT_HANDLER 0x5500
     348        HEAVYWEIGHT_HANDLER 0x5600
     349        HEAVYWEIGHT_HANDLER 0x5700
     350        HEAVYWEIGHT_HANDLER 0x5800
     351        HEAVYWEIGHT_HANDLER 0x5900
     352        HEAVYWEIGHT_HANDLER 0x5a00
     353        HEAVYWEIGHT_HANDLER 0x5b00
     354        HEAVYWEIGHT_HANDLER 0x5c00
     355        HEAVYWEIGHT_HANDLER 0x5d00
     356        HEAVYWEIGHT_HANDLER 0x5e00
     357        HEAVYWEIGHT_HANDLER 0x5f00
     358       
     359        HEAVYWEIGHT_HANDLER 0x6000
     360        HEAVYWEIGHT_HANDLER 0x6100
     361        HEAVYWEIGHT_HANDLER 0x6200
     362        HEAVYWEIGHT_HANDLER 0x6300
     363        HEAVYWEIGHT_HANDLER 0x6400
     364        HEAVYWEIGHT_HANDLER 0x6500
     365        HEAVYWEIGHT_HANDLER 0x6600
     366        HEAVYWEIGHT_HANDLER 0x6700
     367        HEAVYWEIGHT_HANDLER 0x6800
     368        HEAVYWEIGHT_HANDLER 0x6900
     369        HEAVYWEIGHT_HANDLER 0x6a00
     370        HEAVYWEIGHT_HANDLER 0x6b00
     371        HEAVYWEIGHT_HANDLER 0x6c00
     372        HEAVYWEIGHT_HANDLER 0x6d00
     373        HEAVYWEIGHT_HANDLER 0x6e00
     374        HEAVYWEIGHT_HANDLER 0x6f00
     375
     376        HEAVYWEIGHT_HANDLER 0x7000
     377        HEAVYWEIGHT_HANDLER 0x7100
     378        HEAVYWEIGHT_HANDLER 0x7200
     379        HEAVYWEIGHT_HANDLER 0x7300
     380        HEAVYWEIGHT_HANDLER 0x7400
     381        HEAVYWEIGHT_HANDLER 0x7500
     382        HEAVYWEIGHT_HANDLER 0x7600
     383        HEAVYWEIGHT_HANDLER 0x7700
     384        HEAVYWEIGHT_HANDLER 0x7800
     385        HEAVYWEIGHT_HANDLER 0x7900
     386        HEAVYWEIGHT_HANDLER 0x7a00
     387        HEAVYWEIGHT_HANDLER 0x7b00
     388        HEAVYWEIGHT_HANDLER 0x7c00
     389        HEAVYWEIGHT_HANDLER 0x7d00
     390        HEAVYWEIGHT_HANDLER 0x7e00
     391        HEAVYWEIGHT_HANDLER 0x7f00

  • generic/src/main/main.c

    r0b5ac364 re2ec980f  
    162162        arch_post_mm_init();
    163163
    164         printf("%s release %s%s%s\n%s\n", project, release, rr_delimiter, revision, copyright);
     164        printf("%s, release %s%s%s\n%s\n", project, release, rr_delimiter, revision, copyright);
    165165        printf("%P: hardcoded_ktext_size=%dK, hardcoded_kdata_size=%dK\n",
    166166                config.base, hardcoded_ktext_size/1024, hardcoded_kdata_size/1024);
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