Changes in kernel/arch/sparc64/include/mm/sun4u/tlb.h [7a0359b:d99c1d2] in mainline
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kernel/arch/sparc64/include/mm/sun4u/tlb.h (modified) (34 diffs)
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kernel/arch/sparc64/include/mm/sun4u/tlb.h
r7a0359b rd99c1d2 100 100 #include <arch/barrier.h> 101 101 #include <typedefs.h> 102 #include <trace.h>103 102 #include <arch/register.h> 104 103 #include <arch/cpu.h> … … 243 242 * Determine the number of entries in the DMMU's small TLB. 244 243 */ 245 NO_TRACEstatic inline uint16_t tlb_dsmall_size(void)244 static inline uint16_t tlb_dsmall_size(void) 246 245 { 247 246 return 16; … … 251 250 * Determine the number of entries in each DMMU's big TLB. 252 251 */ 253 NO_TRACEstatic inline uint16_t tlb_dbig_size(void)252 static inline uint16_t tlb_dbig_size(void) 254 253 { 255 254 return 512; … … 259 258 * Determine the number of entries in the IMMU's small TLB. 260 259 */ 261 NO_TRACEstatic inline uint16_t tlb_ismall_size(void)260 static inline uint16_t tlb_ismall_size(void) 262 261 { 263 262 return 16; … … 267 266 * Determine the number of entries in the IMMU's big TLB. 268 267 */ 269 NO_TRACEstatic inline uint16_t tlb_ibig_size(void)268 static inline uint16_t tlb_ibig_size(void) 270 269 { 271 270 if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) … … 281 280 * @return Current value of Primary Context Register. 282 281 */ 283 NO_TRACEstatic inline uint64_t mmu_primary_context_read(void)282 static inline uint64_t mmu_primary_context_read(void) 284 283 { 285 284 return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); … … 290 289 * @param v New value of Primary Context Register. 291 290 */ 292 NO_TRACEstatic inline void mmu_primary_context_write(uint64_t v)291 static inline void mmu_primary_context_write(uint64_t v) 293 292 { 294 293 asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); … … 300 299 * @return Current value of Secondary Context Register. 301 300 */ 302 NO_TRACEstatic inline uint64_t mmu_secondary_context_read(void)301 static inline uint64_t mmu_secondary_context_read(void) 303 302 { 304 303 return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); … … 309 308 * @param v New value of Primary Context Register. 310 309 */ 311 NO_TRACEstatic inline void mmu_secondary_context_write(uint64_t v)310 static inline void mmu_secondary_context_write(uint64_t v) 312 311 { 313 312 asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); … … 324 323 * Register. 325 324 */ 326 NO_TRACEstatic inline uint64_t itlb_data_access_read(size_t entry)325 static inline uint64_t itlb_data_access_read(size_t entry) 327 326 { 328 327 itlb_data_access_addr_t reg; … … 338 337 * @param value Value to be written. 339 338 */ 340 NO_TRACEstatic inline void itlb_data_access_write(size_t entry, uint64_t value)339 static inline void itlb_data_access_write(size_t entry, uint64_t value) 341 340 { 342 341 itlb_data_access_addr_t reg; … … 355 354 * Register. 356 355 */ 357 NO_TRACEstatic inline uint64_t dtlb_data_access_read(size_t entry)356 static inline uint64_t dtlb_data_access_read(size_t entry) 358 357 { 359 358 dtlb_data_access_addr_t reg; … … 369 368 * @param value Value to be written. 370 369 */ 371 NO_TRACEstatic inline void dtlb_data_access_write(size_t entry, uint64_t value)370 static inline void dtlb_data_access_write(size_t entry, uint64_t value) 372 371 { 373 372 dtlb_data_access_addr_t reg; … … 385 384 * @return Current value of specified IMMU TLB Tag Read Register. 386 385 */ 387 NO_TRACEstatic inline uint64_t itlb_tag_read_read(size_t entry)386 static inline uint64_t itlb_tag_read_read(size_t entry) 388 387 { 389 388 itlb_tag_read_addr_t tag; … … 400 399 * @return Current value of specified DMMU TLB Tag Read Register. 401 400 */ 402 NO_TRACEstatic inline uint64_t dtlb_tag_read_read(size_t entry)401 static inline uint64_t dtlb_tag_read_read(size_t entry) 403 402 { 404 403 dtlb_tag_read_addr_t tag; … … 420 419 * Register. 421 420 */ 422 NO_TRACEstatic inline uint64_t itlb_data_access_read(int tlb, size_t entry)421 static inline uint64_t itlb_data_access_read(int tlb, size_t entry) 423 422 { 424 423 itlb_data_access_addr_t reg; … … 435 434 * @param value Value to be written. 436 435 */ 437 NO_TRACEstatic inline void itlb_data_access_write(int tlb, size_t entry,436 static inline void itlb_data_access_write(int tlb, size_t entry, 438 437 uint64_t value) 439 438 { … … 455 454 * Register. 456 455 */ 457 NO_TRACEstatic inline uint64_t dtlb_data_access_read(int tlb, size_t entry)456 static inline uint64_t dtlb_data_access_read(int tlb, size_t entry) 458 457 { 459 458 dtlb_data_access_addr_t reg; … … 471 470 * @param value Value to be written. 472 471 */ 473 NO_TRACEstatic inline void dtlb_data_access_write(int tlb, size_t entry,472 static inline void dtlb_data_access_write(int tlb, size_t entry, 474 473 uint64_t value) 475 474 { … … 490 489 * @return Current value of specified IMMU TLB Tag Read Register. 491 490 */ 492 NO_TRACEstatic inline uint64_t itlb_tag_read_read(int tlb, size_t entry)491 static inline uint64_t itlb_tag_read_read(int tlb, size_t entry) 493 492 { 494 493 itlb_tag_read_addr_t tag; … … 507 506 * @return Current value of specified DMMU TLB Tag Read Register. 508 507 */ 509 NO_TRACEstatic inline uint64_t dtlb_tag_read_read(int tlb, size_t entry)508 static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry) 510 509 { 511 510 dtlb_tag_read_addr_t tag; … … 524 523 * @param v Value to be written. 525 524 */ 526 NO_TRACEstatic inline void itlb_tag_access_write(uint64_t v)525 static inline void itlb_tag_access_write(uint64_t v) 527 526 { 528 527 asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); … … 534 533 * @return Current value of IMMU TLB Tag Access Register. 535 534 */ 536 NO_TRACEstatic inline uint64_t itlb_tag_access_read(void)535 static inline uint64_t itlb_tag_access_read(void) 537 536 { 538 537 return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); … … 543 542 * @param v Value to be written. 544 543 */ 545 NO_TRACEstatic inline void dtlb_tag_access_write(uint64_t v)544 static inline void dtlb_tag_access_write(uint64_t v) 546 545 { 547 546 asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); … … 553 552 * @return Current value of DMMU TLB Tag Access Register. 554 553 */ 555 NO_TRACEstatic inline uint64_t dtlb_tag_access_read(void)554 static inline uint64_t dtlb_tag_access_read(void) 556 555 { 557 556 return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); … … 563 562 * @param v Value to be written. 564 563 */ 565 NO_TRACEstatic inline void itlb_data_in_write(uint64_t v)564 static inline void itlb_data_in_write(uint64_t v) 566 565 { 567 566 asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); … … 573 572 * @param v Value to be written. 574 573 */ 575 NO_TRACEstatic inline void dtlb_data_in_write(uint64_t v)574 static inline void dtlb_data_in_write(uint64_t v) 576 575 { 577 576 asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); … … 583 582 * @return Current content of I-SFSR register. 584 583 */ 585 NO_TRACEstatic inline uint64_t itlb_sfsr_read(void)584 static inline uint64_t itlb_sfsr_read(void) 586 585 { 587 586 return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); … … 592 591 * @param v New value of I-SFSR register. 593 592 */ 594 NO_TRACEstatic inline void itlb_sfsr_write(uint64_t v)593 static inline void itlb_sfsr_write(uint64_t v) 595 594 { 596 595 asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); … … 602 601 * @return Current content of D-SFSR register. 603 602 */ 604 NO_TRACEstatic inline uint64_t dtlb_sfsr_read(void)603 static inline uint64_t dtlb_sfsr_read(void) 605 604 { 606 605 return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); … … 611 610 * @param v New value of D-SFSR register. 612 611 */ 613 NO_TRACEstatic inline void dtlb_sfsr_write(uint64_t v)612 static inline void dtlb_sfsr_write(uint64_t v) 614 613 { 615 614 asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); … … 621 620 * @return Current content of D-SFAR register. 622 621 */ 623 NO_TRACEstatic inline uint64_t dtlb_sfar_read(void)622 static inline uint64_t dtlb_sfar_read(void) 624 623 { 625 624 return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); … … 634 633 * @param page Address which is on the page to be demapped. 635 634 */ 636 NO_TRACEstatic inline void itlb_demap(int type, int context_encoding, uintptr_t page)635 static inline void itlb_demap(int type, int context_encoding, uintptr_t page) 637 636 { 638 637 tlb_demap_addr_t da; … … 660 659 * @param page Address which is on the page to be demapped. 661 660 */ 662 NO_TRACEstatic inline void dtlb_demap(int type, int context_encoding, uintptr_t page)661 static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) 663 662 { 664 663 tlb_demap_addr_t da;
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