Changes in boot/arch/arm32/src/asm.S [b5a3b50:cfeb368] in mainline

File:

• boot/arch/arm32/src/asm.S (modified) (1 diff)

boot/arch/arm32/src/asm.S

@@ -61 +61 @@
         #
 
-#if defined(MACHINE_gta02)
+        #
+        # r0 is kernel entry point
+        # r1 is pointer to the bootinfo structure
 
 #define CP15_C1_IC              12
+#define CP15_C1_BP              11
 #define CP15_C1_DC              2
-#define CP15_C7_SEG_SHIFT       5
-#define CP15_C7_SEG_SIZE        3
-#define CP15_C7_IDX_SHIFT       26
-
         # Disable I-cache and D-cache before the kernel is started.
         mrc     p15, 0, r4, c1, c0, 0
         bic     r4, r4, #(1 << CP15_C1_DC)
         bic     r4, r4, #(1 << CP15_C1_IC)
+        bic     r4, r4, #(1 << CP15_C1_BP)
         mcr     p15, 0, r4, c1, c0, 0
+
+        
+        #Wait for the operations to complete
+#ifdef PROCESSOR_ARCH_armv7_a
+        dsb
+#else
+        #cp15 dsb, r4 is ignored (should be zero)
+        mcr p15, 0, r4, c7, c10, 4
+#endif
+        
+        # Clean ICache and BPredictors, r4 ignored (SBZ)
+        mcr p15, 0, r4, c7, c5, 0
+        nop
+
+        #Wait for the operations to complete
+#ifdef PROCESSOR_ARCH_armv7_a
+        isb
+        nop
+#else
+        # cp15 isb
+        mcr p15, 0, r4, c7, c5, 4
+        nop
+#endif
+        
+#TODO:This should not be necessary
+
+#if defined(MACHINE_gta02)
+
+#define CP15_C7_SEG_SHIFT       5
+#define CP15_C7_SEG_SIZE        3
+#define CP15_C7_IDX_SHIFT       26
 
         # Now clean D-cache to guarantee coherency between I-cache and D-cache.