Changeset ce031f0 in mainline


Ignore:
Timestamp:
2005-10-04T11:23:21Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
8e3f47b3
Parents:
1e2aecca
Message:

MIPS work.
Fix some name inconsistencies between cp0 functions' declarations and definitions.
Add and implement tlb_init_arch().
Add tlb_modified() exception handler.

Other architectures: add dummy tlb_init_arch().

Files:
4 added
8 edited

Legend:

Unmodified
Added
Removed

  • arch/mips32/include/cp0.h

    r1e2aecca rce031f0  
    5353#define cp0_compare_value               10000
    5454
    55 static inline void tlbp(void)
    56 {
    57         __asm__ volatile ("tlbp");
    58 }
    59 
    60 static inline void tlbr(void)
    61 {
    62         __asm__ volatile ("tlbr");
    63 }
    64 static inline void tlbwi(void)
    65 {
    66         __asm__ volatile ("tlbwi");
    67 }
    68 static inline void tlbwr(void)
    69 {
    70         __asm__ volatile ("tlbwr");
    71 }
    72 
    7355#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
    7456#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
    … …  
    7658#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
    7759
    78 
    7960extern  __u32 cp0_index_read(void);
    80 extern void cp0_idnex_write(__u32 val);
     61extern void cp0_index_write(__u32 val);
    8162
    8263extern __u32 cp0_random_read(void);

  • arch/mips32/include/mm/tlb.h

    r1e2aecca rce031f0  
    3131
    3232#include <arch/exception.h>
     33
     34#define TLB_SIZE        48
     35
     36#define TLB_WIRED               1
     37#define TLB_KSTACK_WIRED_INDEX  0
     38
     39#define TLB_PAGE_MASK_16K       (0x3<<13)
    3340
    3441#define PAGE_UNCACHED                   2
    … …  
    6673typedef struct entry_lo pte_t;
    6774
     75/** Read Indexed TLB Entry
     76 *
     77 * Read Indexed TLB Entry.
     78 */
     79static inline void tlbr(void)
     80{
     81        __asm__ volatile ("tlbr\n\t");
     82}
     83
     84/** Write Indexed TLB Entry
     85 *
     86 * Write Indexed TLB Entry.
     87 */
     88static inline void tlbwi(void)
     89{
     90        __asm__ volatile ("tlbwi\n\t");
     91}
     92
     93/** Write Random TLB Entry
     94 *
     95 * Write Random TLB Entry.
     96 */
     97static inline void tlbwr(void)
     98{
     99        __asm__ volatile ("tlbwr\n\t");
     100}
     101
    68102extern void tlb_invalid(struct exception_regdump *pstate);
    69103extern void tlb_refill(struct exception_regdump *pstate);
     104extern void tlb_modified(struct exception_regdump *pstate);
    70105
    71106#endif

  • arch/mips32/src/asm.S

    r1e2aecca rce031f0  
    6363.global cp0_count_read
    6464.global cp0_count_write
    65 .global cp0_hi_read
    66 .global cp0_hi_write
     65.global cp0_entry_hi_read
     66.global cp0_entry_hi_write
    6767.global cp0_compare_read
    6868.global cp0_compare_write

  • arch/mips32/src/exception.c

    r1e2aecca rce031f0  
    8181                        break;
    8282                case EXC_Mod:
    83                         panic("unhandled TLB Modification Exception\n");
     83                        tlb_modified(pstate);
    8484                        break;
    8585                case EXC_AdEL:

  • arch/mips32/src/mm/tlb.c

    r1e2aecca rce031f0  
    3333#include <panic.h>
    3434#include <arch.h>
     35#include <symtab.h>
    3536
    36 #include <symtab.h>
     37void tlb_init_arch(void)
     38{
     39        int i;
     40
     41        cp0_pagemask_write(TLB_PAGE_MASK_16K);
     42        cp0_entry_hi_write(0);
     43        cp0_entry_lo0_write(0);
     44        cp0_entry_lo1_write(0);
     45
     46        /*
     47         * Invalidate all entries.
     48         */
     49        for (i = 0; i < TLB_SIZE; i++) {
     50                cp0_index_write(0);
     51                tlbwi();
     52        }
     53       
     54        /*
     55         * The kernel is going to make use of some wired
     56         * entries (e.g. mapping kernel stacks).
     57         */
     58        cp0_wired_write(TLB_WIRED);
     59}
    3760
    3861void tlb_refill(struct exception_regdump *pstate)
    … …  
    4770        if (s)
    4871                sym2 = s;
    49         panic("%X: tlb_refill exception at %X(%s<-%s)\n", cp0_badvaddr_read(),
    50               pstate->epc, symbol,sym2);
     72        panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(),
     73              pstate->epc, symbol, sym2);
    5174}
    5275
    … …  
    5881        if (s)
    5982                symbol = s;
    60         panic("%X: TLB exception at %X(%s)\n", cp0_badvaddr_read(),
     83        panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(),
    6184              pstate->epc, symbol);
    6285}
     86
     87void tlb_modified(struct exception_regdump *pstate)
     88{
     89        char *symbol = "";
     90
     91        char *s = get_symtab_entry(pstate->epc);
     92        if (s)
     93                symbol = s;
     94        panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(),
     95              pstate->epc, symbol);
     96}
     97
    6398
    6499void tlb_invalidate(int asid)

  • include/mm/tlb.h

    r1e2aecca rce031f0  
    3030#define __TLB_H__
    3131
     32extern void tlb_init(void);
     33
    3234#ifdef __SMP__
    33 extern void tlb_init(void);
    3435extern void tlb_shootdown_start(void);
    3536extern void tlb_shootdown_finalize(void);
    3637extern void tlb_shootdown_ipi_recv(void);
    3738#else
    38 
    39 #define tlb_init()              ;
    40 #define tlb_shootdown_start()   ;
    41 #define tlb_shootdown_finalize()        ;
    42 #define tlb_shootdown_ipi_recv() ;
    43 
     39#  define tlb_shootdown_start() ;
     40#  define tlb_shootdown_finalize()      ;
     41#  define tlb_shootdown_ipi_recv() ;
    4442#endif /* __SMP__ */
    4543
    4644/* Export TLB interface that each architecture must implement. */
     45extern void tlb_init_arch(void);
    4746extern void tlb_invalidate(int asid);
    4847extern void tlb_shootdown_ipi_send(void);

  • src/main/main.c

    r1e2aecca rce031f0  
    152152        page_init();
    153153        tlb_init();
    154 
    155154        arch_post_mm_init();
    156155
    … …  
    231230        frame_init();
    232231        page_init();
     232        tlb_init();
    233233        arch_post_mm_init();
    234234       

  • src/mm/tlb.c

    r1e2aecca rce031f0  
    2828
    2929#include <mm/tlb.h>
     30#include <arch/mm/tlb.h>
    3031#include <smp/ipi.h>
    3132#include <synch/spinlock.h>
    … …  
    3839#ifdef __SMP__
    3940static spinlock_t tlblock;
     41#endif
    4042
    4143void tlb_init(void)
    4244{
    43         spinlock_initialize(&tlblock);
     45        if (config.cpu_active == 1)
     46                spinlock_initialize(&tlblock);
     47
     48        tlb_init_arch();
    4449}
    4550
     51#ifdef __SMP__
    4652/* must be called with interrupts disabled */
    4753void tlb_shootdown_start(void)
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