Changeset caed0279 in mainline

Timestamp:

2012-05-05T13:24:58Z (12 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

1295a1da

Parents:

ee04c28

Message:

Fix computation of the address increment between two PTL0 entries.

The previous computation divided the theoretical address space size
(either 2^{32 or 2}64 bytes) by the number of PTL0 entries. This,
however, provides wrong results on some 64-bit architectures that use
smaller virtual address spaces. For example, amd64 has only 48-bit
virtual address space and so the computation needs to take this into
account.

File:

• kernel/genarch/src/mm/page_pt.c (modified) (4 diffs)

kernel/genarch/src/mm/page_pt.c

@@ -48 +48 @@
 #include <align.h>
 #include <macros.h>
+#include <bitops.h>
 
 static void pt_mapping_insert(as_t *, uintptr_t, uintptr_t, unsigned int);
@@ -292 +293 @@
 }
 
+/** Return the size of the region mapped by a single PTL0 entry.
+ *
+ * @return Size of the region mapped by a single PTL0 entry.
+ */
+static uintptr_t ptl0_step_get(void)
+{
+        size_t va_bits;
+
+        va_bits = fnzb(PTL0_ENTRIES) + fnzb(PTL1_ENTRIES) + fnzb(PTL2_ENTRIES) +
+            fnzb(PTL3_ENTRIES) + PAGE_WIDTH;
+
+        return 1UL << (va_bits - fnzb(PTL0_ENTRIES));
+}
+
 /** Make the mappings in the given range global accross all address spaces.
  *
@@ -309 +324 @@
 {
         uintptr_t ptl0 = PA2KA((uintptr_t) AS_KERNEL->genarch.page_table);
-        uintptr_t ptl0step = (((uintptr_t) -1) / PTL0_ENTRIES) + 1;
+        uintptr_t ptl0_step = ptl0_step_get();
         size_t order;
         uintptr_t addr;
@@ -321 +336 @@
 #endif
 
-        ASSERT(ispwr2(ptl0step));
         ASSERT(size > 0);
 
-        for (addr = ALIGN_DOWN(base, ptl0step); addr - 1 < base + size - 1;
-            addr += ptl0step) {
+        for (addr = ALIGN_DOWN(base, ptl0_step); addr - 1 < base + size - 1;
+            addr += ptl0_step) {
                 uintptr_t l1;