Changes in kernel/arch/sparc64/include/barrier.h [723060a:c8e99bb] in mainline

File:

• kernel/arch/sparc64/include/barrier.h (modified) (3 diffs)

kernel/arch/sparc64/include/barrier.h

@@ -36 +36 @@
 #define KERN_sparc64_BARRIER_H_
 
+#ifdef KERNEL
+#include <typedefs.h>
+#else
+#include <stdint.h>
+#endif
+
 /*
  * Our critical section barriers are prepared for the weakest RMO memory model.
@@ -64 +70 @@
 static inline void flush_pipeline(void)
 {
+        uint64_t pc;
+
         /*
          * The FLUSH instruction takes address parameter.
@@ -70 +78 @@
          * The entire kernel text is mapped by a locked ITLB and
          * DTLB entries. Therefore, when this function is called,
-         * the %o7 register will always be in the range mapped by
+         * the %pc register will always be in the range mapped by
          * DTLB.
          */
          
-        asm volatile ("flush %o7\n");
+        asm volatile (
+                "rd %%pc, %0\n"
+                "flush %0\n"
+                : "=&r" (pc)
+        );
 }