Changeset bea6233 in mainline

Timestamp:

2023-02-26T15:27:13Z (15 months ago)

Author:

Jiří Zárevúcky <zarevucky.jiri@…>

Branches:

master, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

7cf5ddb

Parents:

deed510

git-author:

Jiří Zárevúcky <zarevucky.jiri@…> (2023-02-26 15:18:02)

git-committer:

Jiří Zárevúcky <zarevucky.jiri@…> (2023-02-26 15:27:13)

Message:

Replace cpu_sleep() with cpu_interruptible_sleep()

The new function combines interrupt reenabling with sleep,
so that a platform can implement this sequence atomically.
This is currently done only on ia32 and amd64.

Location:

kernel

Files:

• arch/abs32le/include/arch/asm.h (modified) (1 diff)
• arch/amd64/include/arch/asm.h (modified) (1 diff)
• arch/arm32/include/arch/asm.h (modified) (1 diff)
• arch/arm64/include/arch/asm.h (modified) (1 diff)
• arch/ia32/include/arch/asm.h (modified) (1 diff)
• arch/ia64/include/arch/asm.h (modified) (1 diff)
• arch/mips32/include/arch/asm.h (modified) (1 diff)
• arch/ppc32/include/arch/asm.h (modified) (1 diff)
• arch/riscv64/include/arch/asm.h (modified) (1 diff)
• arch/sparc64/include/arch/asm.h (modified) (1 diff)
• generic/src/proc/scheduler.c (modified) (2 diffs)

kernel/arch/abs32le/include/arch/asm.h

@@ -197 +197 @@
 }
 
+/** Enables interrupts and blocks until an interrupt arrives,
+ * atomically if possible on target architecture.
+ * Disables interrupts again before returning to caller.
+ */
+_NO_TRACE static inline void cpu_interruptible_sleep(void)
+{
+        interrupts_enable();
+        cpu_sleep();
+        interrupts_disable();
+}
+
 #endif
 

kernel/arch/amd64/include/arch/asm.h

@@ -43 +43 @@
 #define IO_SPACE_BOUNDARY       ((void *) (64 * 1024))
 
-_NO_TRACE static inline void cpu_sleep(void)
-{
-        asm volatile (
+/** Enables interrupts and blocks until an interrupt arrives,
+ * atomically if possible on target architecture.
+ * Disables interrupts again before returning to caller.
+ */
+_NO_TRACE static inline void cpu_interruptible_sleep()
+{
+        /*
+         * On x86, "sti" enables interrupts after the next instruction.
+         * Therefore, this sequence is guaranteed to be atomic.
+         */
+        asm volatile (
+            "sti\n"
             "hlt\n"
+            "cli\n"
         );
 }

kernel/arch/arm32/include/arch/asm.h

@@ -65 +65 @@
 }
 
+/** Enables interrupts and blocks until an interrupt arrives,
+ * atomically if possible on target architecture.
+ * Disables interrupts again before returning to caller.
+ */
+_NO_TRACE static inline void cpu_interruptible_sleep(void)
+{
+        // FIXME: do this atomically
+        interrupts_enable();
+        cpu_sleep();
+        interrupts_disable();
+}
+
 _NO_TRACE static inline void cpu_spin_hint(void)
 {

kernel/arch/arm64/include/arch/asm.h

@@ -52 +52 @@
 {
         asm volatile ("wfe");
+}
+
+/** Enables interrupts and blocks until an interrupt arrives,
+ * atomically if possible on target architecture.
+ * Disables interrupts again before returning to caller.
+ */
+_NO_TRACE static inline void cpu_interruptible_sleep(void)
+{
+        // FIXME: do this atomically
+        interrupts_enable();
+        cpu_sleep();
+        interrupts_disable();
 }
 

kernel/arch/ia32/include/arch/asm.h

@@ -57 +57 @@
 }
 
-_NO_TRACE static inline void cpu_sleep(void)
-{
-        asm volatile (
+/** Enables interrupts and blocks until an interrupt arrives,
+ * atomically if possible on target architecture.
+ * Disables interrupts again before returning to caller.
+ */
+_NO_TRACE static inline void cpu_interruptible_sleep(void)
+{
+        asm volatile (
+            "sti\n"
             "hlt\n"
+            "cli\n"
         );
 }

kernel/arch/ia64/include/arch/asm.h

@@ -473 +473 @@
     uint64_t, uint64_t);
 
+/** Enables interrupts and blocks until an interrupt arrives,
+ * atomically if possible on target architecture.
+ * Disables interrupts again before returning to caller.
+ */
+_NO_TRACE static inline void cpu_interruptible_sleep(void)
+{
+        // FIXME: do this properly
+        interrupts_enable();
+        cpu_sleep();
+        interrupts_disable();
+}
+
 #endif
 

kernel/arch/mips32/include/arch/asm.h

@@ -89 +89 @@
 extern bool interrupts_disabled(void);
 
+/** Enables interrupts and blocks until an interrupt arrives,
+ * atomically if possible on target architecture.
+ * Disables interrupts again before returning to caller.
+ */
+_NO_TRACE static inline void cpu_interruptible_sleep(void)
+{
+        // FIXME: do this atomically
+        interrupts_enable();
+        cpu_sleep();
+        interrupts_disable();
+}
+
 #endif
 

kernel/arch/ppc32/include/arch/asm.h

@@ -167 +167 @@
 }
 
-_NO_TRACE static inline void cpu_sleep(void)
-{
+/** Enables interrupts and blocks until an interrupt arrives,
+ * atomically if possible on target architecture.
+ * Disables interrupts again before returning to caller.
+ */
+_NO_TRACE static inline void cpu_interruptible_sleep(void)
+{
+        // FIXME: do this properly
+        interrupts_enable();
+        interrupts_disable();
 }
 

kernel/arch/riscv64/include/arch/asm.h

@@ -95 +95 @@
 }
 
-_NO_TRACE static inline void cpu_sleep(void)
+/** Enables interrupts and blocks until an interrupt arrives,
+ * atomically if possible on target architecture.
+ * Disables interrupts again before returning to caller.
+ */
+_NO_TRACE static inline void cpu_interruptible_sleep(void)
 {
+        // FIXME: do this properly
+        interrupts_enable();
+        interrupts_disable();
 }
 

kernel/arch/sparc64/include/arch/asm.h

@@ -539 +539 @@
 extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);
 
+/** Enables interrupts and blocks until an interrupt arrives,
+ * atomically if possible on target architecture.
+ * Disables interrupts again before returning to caller.
+ */
+_NO_TRACE static inline void cpu_interruptible_sleep(void)
+{
+        // FIXME: do this atomically
+        interrupts_enable();
+        cpu_sleep();
+        interrupts_disable();
+}
+
 #endif
 

kernel/generic/src/proc/scheduler.c

@@ -187 +187 @@
 
 loop:
-
         if (atomic_load(&CPU->nrdy) == 0) {
                 /*
@@ -197 +196 @@
                 CPU->idle = true;
                 irq_spinlock_unlock(&CPU->lock, false);
-                interrupts_enable();
 
                 /*
-                 * An interrupt might occur right now and wake up a thread.
-                 * In such case, the CPU will continue to go to sleep
-                 * even though there is a runnable thread.
+                 * Go to sleep with interrupts enabled.
+                 * Ideally, this should be atomic, but this is not guaranteed on
+                 * all platforms yet, so it is possible we will go sleep when
+                 * a thread has just become available.
                  */
-                cpu_sleep();
-                interrupts_disable();
+                cpu_interruptible_sleep();
+
+                /* Interrupts are disabled again. */
                 goto loop;
         }