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  • kernel/arch/sparc64/src/trap/sun4v/trap_table.S

    rf8f7dba rba50a34  
    4848#include <arch/stack.h>
    4949#include <arch/sun4v/regdef.h>
    50 #include <arch/sun4v/arch.h>
    51 #include <arch/sun4v/cpu.h>
    5250
    5351#define TABLE_SIZE      TRAP_TABLE_SIZE
    … …  
    6260
    6361/* TT = 0x08, TL = 0, instruction_access_exception */
    64 /* TT = 0x08, TL = 0, IAE_privilege_violation on UltraSPARC T2 */
    6562.org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE
    6663.global instruction_access_exception_tl0
    6764instruction_access_exception_tl0:
    68         PREEMPTIBLE_HANDLER instruction_access_exception
    69 
    70 /* TT = 0x09, TL = 0, instruction_access_mmu_miss */
    71 .org trap_table + TT_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE
    72 .global instruction_access_mmu_miss_handler_tl0
    73         ba fast_instruction_access_mmu_miss_handler_tl0
    74         nop
     65        /*wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
     66        PREEMPTIBLE_HANDLER instruction_access_exception*/
    7567
    7668/* TT = 0x0a, TL = 0, instruction_access_error */
    … …  
    8072        PREEMPTIBLE_HANDLER instruction_access_error
    8173
    82 /* TT = 0x0b, TL = 0, IAE_unauth_access */
    83 .org trap_table + TT_IAE_UNAUTH_ACCESS*ENTRY_SIZE
    84 .global iae_unauth_access_tl0
    85 iae_unauth_access_tl0:
    86         PREEMPTIBLE_HANDLER instruction_access_exception
    87 
    88 /* TT = 0x0c, TL = 0, IAE_nfo_page */
    89 .org trap_table + TT_IAE_NFO_PAGE*ENTRY_SIZE
    90 .global iae_nfo_page_tl0
    91 iae_nfo_page_tl0:
    92         PREEMPTIBLE_HANDLER instruction_access_exception
    93 
    9474/* TT = 0x10, TL = 0, illegal_instruction */
    9575.org trap_table + TT_ILLEGAL_INSTRUCTION*ENTRY_SIZE
    … …  
    11696        PREEMPTIBLE_HANDLER unimplemented_STD
    11797
    118 /* TT = 0x14, TL = 0, DAE_invalid_asi */
    119 .org trap_table + TT_DAE_INVALID_ASI*ENTRY_SIZE
    120 .global dae_invalid_asi_tl0
    121 dae_invalid_asi_tl0:
    122         PREEMPTIBLE_HANDLER data_access_exception
    123 
    124 /* TT = 0x15, TL = 0, DAE_privilege_violation */
    125 .org trap_table + TT_DAE_PRIVILEGE_VIOLATION*ENTRY_SIZE
    126 .global dae_privilege_violation_tl0
    127 dae_privilege_violation_tl0:
    128         PREEMPTIBLE_HANDLER data_access_exception
    129 
    130 /* TT = 0x16, TL = 0, DAE_nc_page */
    131 .org trap_table + TT_DAE_NC_PAGE*ENTRY_SIZE
    132 .global dae_nc_page_tl0
    133 dae_nc_page_tl0:
    134         PREEMPTIBLE_HANDLER data_access_exception
    135 
    136 /* TT = 0x17, TL = 0, DAE_nfo_page */
    137 .org trap_table + TT_DAE_NFO_PAGE*ENTRY_SIZE
    138 .global dae_nfo_page_tl0
    139 dae_nfo_page_tl0:
    140         PREEMPTIBLE_HANDLER data_access_exception
    141 
    14298/* TT = 0x20, TL = 0, fb_disabled handler */
    14399.org trap_table + TT_FP_DISABLED*ENTRY_SIZE
    … …  
    177133
    178134/* TT = 0x30, TL = 0, data_access_exception */
    179 /* TT = 0x30, TL = 0, DAE_side_effect_page for UltraPSARC T2 */
    180135.org trap_table + TT_DATA_ACCESS_EXCEPTION*ENTRY_SIZE
    181136.global data_access_exception_tl0
    182137data_access_exception_tl0:
     138        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    183139        PREEMPTIBLE_HANDLER data_access_exception
    184 
    185 /* TT = 0x31, TL = 0, data_access_mmu_miss */
    186 .org trap_table + TT_DATA_ACCESS_MMU_MISS*ENTRY_SIZE
    187 .global data_access_mmu_miss_tl0
    188 data_access_mmu_miss_tl0:
    189         ba fast_data_access_mmu_miss_handler_tl0
    190         nop
    191140
    192141/* TT = 0x32, TL = 0, data_access_error */
    … …  
    322271        INTERRUPT_LEVEL_N_HANDLER 15
    323272
     273/* TT = 0x60, TL = 0, interrupt_vector_trap handler */
     274.org trap_table + TT_INTERRUPT_VECTOR_TRAP*ENTRY_SIZE
     275.global interrupt_vector_trap_handler_tl0
     276interrupt_vector_trap_handler_tl0:
     277        INTERRUPT_VECTOR_TRAP_HANDLER
     278
    324279/* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */
    325280.org trap_table + TT_FAST_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE
    … …  
    339294fast_data_access_protection_handler_tl0:
    340295        FAST_DATA_ACCESS_PROTECTION_HANDLER 0
    341 
    342 /* TT = 0x7c, TL = 0, cpu_mondo */
    343 .org trap_table + TT_CPU_MONDO*ENTRY_SIZE
    344 .global cpu_mondo_handler_tl0
    345 cpu_mondo_handler_tl0:
    346 PREEMPTIBLE_HANDLER cpu_mondo
    347296
    348297/* TT = 0x80, TL = 0, spill_0_normal handler */
    … …  
    403352
    404353/* TT = 0x08, TL > 0, instruction_access_exception */
    405 /* TT = 0x08, TL > 0, IAE_privilege_violation on UltraSPARC T2 */
    406354.org trap_table + (TT_INSTRUCTION_ACCESS_EXCEPTION+512)*ENTRY_SIZE
    407355.global instruction_access_exception_tl1
    408356instruction_access_exception_tl1:
    409357        wrpr %g0, 1, %tl
     358        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    410359        PREEMPTIBLE_HANDLER instruction_access_exception
    411 
    412 /* TT = 0x09, TL > 0, instruction_access_mmu_miss */
    413 .org trap_table + (TT_INSTRUCTION_ACCESS_MMU_MISS+512)*ENTRY_SIZE
    414 .global instruction_access_mmu_miss_handler_tl1
    415         wrpr %g0, 1, %tl
    416         ba fast_instruction_access_mmu_miss_handler_tl0
    417         nop
    418360
    419361/* TT = 0x0a, TL > 0, instruction_access_error */
    … …  
    424366        PREEMPTIBLE_HANDLER instruction_access_error
    425367
    426 /* TT = 0x0b, TL > 0, IAE_unauth_access */
    427 .org trap_table + (TT_IAE_UNAUTH_ACCESS+512)*ENTRY_SIZE
    428 .global iae_unauth_access_tl1
    429 iae_unauth_access_tl1:
    430         wrpr %g0, 1, %tl
    431         PREEMPTIBLE_HANDLER instruction_access_exception
    432 
    433 /* TT = 0x0c, TL > 0, IAE_nfo_page */
    434 .org trap_table + (TT_IAE_NFO_PAGE+512)*ENTRY_SIZE
    435 .global iae_nfo_page_tl1
    436 iae_nfo_page_tl1:
    437         wrpr %g0, 1, %tl
    438         PREEMPTIBLE_HANDLER instruction_access_exception
    439 
    440368/* TT = 0x10, TL > 0, illegal_instruction */
    441369.org trap_table + (TT_ILLEGAL_INSTRUCTION+512)*ENTRY_SIZE
    … …  
    445373        PREEMPTIBLE_HANDLER illegal_instruction
    446374
    447 /* TT = 0x14, TL > 0, DAE_invalid_asi */
    448 .org trap_table + (TT_DAE_INVALID_ASI+512)*ENTRY_SIZE
    449 .global dae_invalid_asi_tl1
    450 dae_invalid_asi_tl1:
    451         wrpr %g0, 1, %tl
    452         PREEMPTIBLE_HANDLER data_access_exception
    453 
    454 /* TT = 0x15, TL > 0, DAE_privilege_violation */
    455 .org trap_table + (TT_DAE_PRIVILEGE_VIOLATION+512)*ENTRY_SIZE
    456 .global dae_privilege_violation_tl1
    457 dae_privilege_violation_tl1:
    458         wrpr %g0, 1, %tl
    459         PREEMPTIBLE_HANDLER data_access_exception
    460 
    461 /* TT = 0x16, TL > 0, DAE_nc_page */
    462 .org trap_table + (TT_DAE_NC_PAGE+512)*ENTRY_SIZE
    463 .global dae_nc_page_tl1
    464 dae_nc_page_tl1:
    465         wrpr %g0, 1, %tl
    466         PREEMPTIBLE_HANDLER data_access_exception
    467 
    468 /* TT = 0x17, TL > 0, DAE_nfo_page */
    469 .org trap_table + (TT_DAE_NFO_PAGE+512)*ENTRY_SIZE
    470 .global dae_nfo_page_tl1
    471 dae_nfo_page_tl1:
    472         wrpr %g0, 1, %tl
    473         PREEMPTIBLE_HANDLER data_access_exception
    474 
    475375/* TT = 0x24, TL > 0, clean_window handler */
    476376.org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE
    … …  
    490390.global data_access_exception_tl1
    491391data_access_exception_tl1:
    492         /*wrpr %g0, 1, %tl
     392        wrpr %g0, 1, %tl
    493393        wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
    494         PREEMPTIBLE_HANDLER data_access_exception*/
    495 
    496 /* TT = 0x31, TL > 0, data_access_mmu_miss */
    497 .org trap_table + (TT_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE
    498 .global data_access_mmu_miss_tl1
    499 data_access_mmu_miss_tl1:
    500         ba fast_data_access_mmu_miss_handler_tl1
    501         nop
    502 
     394        PREEMPTIBLE_HANDLER data_access_exception
    503395
    504396/* TT = 0x32, TL > 0, data_access_error */
    … …  
    527419fast_data_access_protection_handler_tl1:
    528420        FAST_DATA_ACCESS_PROTECTION_HANDLER 1
    529 
    530 /* TT = 0x7c, TL > 0, cpu_mondo */
    531 .org trap_table + (TT_CPU_MONDO+512)*ENTRY_SIZE
    532 .global cpu_mondo_handler_tl1
    533 cpu_mondo_handler_tl1:
    534         wrpr %g0, %tl
    535         PREEMPTIBLE_HANDLER cpu_mondo
    536421
    537422/* TT = 0x80, TL > 0, spill_0_normal handler */
    … …  
    775660.endm
    776661
     662
     663#if 0
    777664/*
    778665 * Preemptible trap handler for handling traps from kernel.
    … …  
    790677        nop                                     ! it will be easy to find
    791678
     679        /* prevent unnecessary CLEANWIN exceptions */
     680        wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(0), %wstate
     6811:
     682        /*
     683         * Prevent SAVE instruction from causing a spill exception. If the
     684         * CANSAVE register is zero, explicitly spill register window
     685         * at CWP + 2.
     686         */
     687
     688        rdpr %cansave, %g3
     689        brnz %g3, 2f
     690        nop
     691        INLINE_SPILL %g3, %g4
     692
     6932:
     694        /* ask for new register window */
     695        save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
     696
     697        /* copy higher level routine's address and its argument */
     698        mov %g1, %l0
     699        mov %g2, %o0
     700
     701        /*
     702         * Save TSTATE, TPC and TNPC aside.
     703         */
     704        rdpr %tstate, %g1
     705        rdpr %tpc, %g2
     706        rdpr %tnpc, %g3
     707
     708        stx %g1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE]
     709        stx %g2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC]
     710        stx %g3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC]
     711
     712        /*
     713         * Save the Y register.
     714         * This register is deprecated according to SPARC V9 specification
     715         * and is only present for backward compatibility with previous
     716         * versions of the SPARC architecture.
     717         * Surprisingly, gcc makes use of this register without a notice.
     718         */
     719        rd %y, %g4
     720        stx %g4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y]
     721
     722        /* switch to TL = 0, explicitly enable FPU */
     723        wrpr %g0, 0, %tl
     724        wrpr %g0, 0, %gl
     725        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT, %pstate
     726
     727        /* g1 -> l1, ..., g7 -> l7 */
     728        SAVE_GLOBALS
     729
     730        /* call higher-level service routine, pass istate as its 2nd parameter */
     731        call %l0
     732        add %sp, PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC, %o1
     733
     734        /* l1 -> g1, ..., l7 -> g7 */
     735        RESTORE_GLOBALS
     736
     737        /* we must prserve the PEF bit */
     738        rdpr %pstate, %l1
     739
     740        /* TL := 1, GL := 1 */
     741        wrpr %g0, PSTATE_PRIV_BIT, %pstate
     742        wrpr %g0, 1, %tl
     743        wrpr %g0, 1, %gl
     744
     745        /* Read TSTATE, TPC and TNPC from saved copy. */
     746        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE], %g1
     747        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC], %g2
     748        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC], %g3
     749
     750        /* Copy PSTATE.PEF to the in-register copy of TSTATE. */
     751        and %l1, PSTATE_PEF_BIT, %l1
     752        sllx %l1, TSTATE_PSTATE_SHIFT, %l1
     753        sethi %hi(TSTATE_PEF_BIT), %g4          ! reset the PEF bit to 0 ...
     754        andn %g1, %g4, %g1
     755        or %g1, %l1, %g1                        ! ... "or" it with saved PEF
     756
     757        /* Restore TSTATE, TPC and TNPC from saved copies. */
     758        wrpr %g1, 0, %tstate
     759        wrpr %g2, 0, %tpc
     760        wrpr %g3, 0, %tnpc
     761
     762        /* Restore Y. */
     763        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y], %g4
     764        wr %g4, %y
     765       
     766        /* If TSTATE.CWP + 1 == CWP, then we do not have to fix CWP. */
     767        and %g1, TSTATE_CWP_MASK, %l0
     768        inc %l0
     769        and %l0, NWINDOWS - 1, %l0      ! %l0 mod NWINDOWS
     770        rdpr %cwp, %l1
     771        cmp %l0, %l1
     772        bz 4f                           ! CWP is ok
     773        nop
     774
     7753:
     776        /*
     777         * Fix CWP.
     778         * In order to recapitulate, the input registers in the current
     779         * window are the output registers of the window to which we want
     780         * to restore. Because the fill trap fills only input and local
     781         * registers of a window, we need to preserve those output
     782         * registers manually.
     783         */
     784        mov %sp, %g2
     785        stx %i0, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0]
     786        stx %i1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1]
     787        stx %i2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2]
     788        stx %i3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3]
     789        stx %i4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4]
     790        stx %i5, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5]
     791        stx %i6, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6]
     792        stx %i7, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7]
     793        wrpr %l0, 0, %cwp
     794        mov %g2, %sp
     795        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0], %i0
     796        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1], %i1
     797        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2], %i2
     798        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3], %i3
     799        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4], %i4
     800        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5], %i5
     801        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6], %i6
     802        ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7], %i7
     803
     8044:
     805        /*
     806         * Prevent RESTORE instruction from causing a fill exception. If the
     807         * CANRESTORE register is zero, explicitly fill register window
     808         * at CWP - 1.
     809         */
     810        rdpr %canrestore, %g1
     811        brnz %g1, 5f
     812        nop
     813        INLINE_FILL %g3, %g4
     814
     8155:
     816        restore
     817
     818        retry
     819.endm
     820
     821#endif
     822
     823/*
     824 * Preemptible trap handler for handling traps from kernel.
     825 */
     826.macro PREEMPTIBLE_HANDLER_KERNEL
     827
     828        /*
     829         * ASSERT(%tl == 1)
     830         */
     831        rdpr %tl, %g3
     832        cmp %g3, 1
     833        be 1f
     834        nop
     8350:      ba 0b                                   ! this is for debugging, if we ever get here
     836        nop                                     ! it will be easy to find
     837
    7928381:
    793839        /* prevent unnecessary CLEANWIN exceptions */
    … …  
    826872        retry
    827873.endm
     874
     875
    828876
    829877/*
    … …  
    10441092        and %g1, NWINDOWS - 1, %g1
    10451093        wrpr %g1, 0, %cwp                       ! CWP--
    1046        
     1094
    10471095.if \is_syscall
    10481096        done
    … …  
    10521100
    10531101.endm
     1102
     1103
    10541104
    10551105/* Preemptible trap handler for TL=1.
    … …  
    10821132trap_instruction_handler:
    10831133        PREEMPTIBLE_HANDLER_TEMPLATE 1
     1134
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