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Changeset b8e56d9b in mainline


Ignore:
Timestamp:
2012-03-07T21:05:56Z (10 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master
Children:
590ce352
Parents:
81c354f
Message:

amdm37x, gpt: Add irq information, implement simple tick timer driver.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/genarch/include/drivers/amdm37x_gpt/amdm37x_gpt.h

    r81c354f rb8e56d9b  
    3737#define KERN_AMDM37x_GPT_H_
    3838
     39#include <typedefs.h>
     40#include <mm/km.h>
     41
    3942/* AMDM37x TRM p. 2740 */
    40 #define AMDM37x_GPT1_BASE_ADDRESS 0x48318000
    41 #define AMDM37x_GPT1_SIZE 4096
    42 #define AMDM37x_GPT2_BASE_ADDRESS 0x49032000
    43 #define AMDM37x_GPT2_SIZE 4096
    44 #define AMDM37x_GPT3_BASE_ADDRESS 0x49034000
    45 #define AMDM37x_GPT3_SIZE 4096
    46 #define AMDM37x_GPT4_BASE_ADDRESS 0x49036000
    47 #define AMDM37x_GPT4_SIZE 4096
    48 #define AMDM37x_GPT5_BASE_ADDRESS 0x49038000
    49 #define AMDM37x_GPT5_SIZE 4096
    50 #define AMDM37x_GPT6_BASE_ADDRESS 0x4903a000
    51 #define AMDM37x_GPT6_SIZE 4096
    52 #define AMDM37x_GPT7_BASE_ADDRESS 0x4903c000
    53 #define AMDM37x_GPT7_SIZE 4096
    54 #define AMDM37x_GPT8_BASE_ADDRESS 0x4903e000
    55 #define AMDM37x_GPT8_SIZE 4096
    56 #define AMDM37x_GPT9_BASE_ADDRESS 0x49040000
    57 #define AMDM37x_GPT9_SIZE 4096
    58 #define AMDM37x_GPT10_BASE_ADDRESS 0x48086000
    59 #define AMDM37x_GPT10_SIZE 4096
    60 #define AMDM37x_GPT11_BASE_ADDRESS 0x48088000
    61 #define AMDM37x_GPT11_SIZE 4096
    62 
    63 #include <typedefs.h>
     43#define AMDM37x_GPT1_BASE_ADDRESS  0x48318000
     44#define AMDM37x_GPT1_SIZE  4096
     45#define AMDM37x_GPT1_IRQ  37
     46#define AMDM37x_GPT2_BASE_ADDRESS  0x49032000
     47#define AMDM37x_GPT2_SIZE  4096
     48#define AMDM37x_GPT2_IRQ  38
     49#define AMDM37x_GPT3_BASE_ADDRESS  0x49034000
     50#define AMDM37x_GPT3_SIZE  4096
     51#define AMDM37x_GPT3_IRQ  39
     52#define AMDM37x_GPT4_BASE_ADDRESS  0x49036000
     53#define AMDM37x_GPT4_SIZE  4096
     54#define AMDM37x_GPT4_IRQ  40
     55#define AMDM37x_GPT5_BASE_ADDRESS  0x49038000
     56#define AMDM37x_GPT5_SIZE  4096
     57#define AMDM37x_GPT5_IRQ  41
     58#define AMDM37x_GPT6_BASE_ADDRESS  0x4903a000
     59#define AMDM37x_GPT6_SIZE  4096
     60#define AMDM37x_GPT6_IRQ  42
     61#define AMDM37x_GPT7_BASE_ADDRESS  0x4903c000
     62#define AMDM37x_GPT7_SIZE  4096
     63#define AMDM37x_GPT7_IRQ  43
     64#define AMDM37x_GPT8_BASE_ADDRESS  0x4903e000
     65#define AMDM37x_GPT8_SIZE  4096
     66#define AMDM37x_GPT8_IRQ  44
     67#define AMDM37x_GPT9_BASE_ADDRESS  0x49040000
     68#define AMDM37x_GPT9_SIZE  4096
     69#define AMDM37x_GPT9_IRQ  45
     70#define AMDM37x_GPT10_BASE_ADDRESS  0x48086000
     71#define AMDM37x_GPT10_SIZE  4096
     72#define AMDM37x_GPT10_IRQ  46
     73#define AMDM37x_GPT11_BASE_ADDRESS  0x48088000
     74#define AMDM37x_GPT11_SIZE  4096
     75#define AMDM37x_GPT11_IRQ  47
     76
    6477
    6578/** GPT register map AMDM37x TRM p. 2740 */
     
    177190} amdm37x_gpt_regs_t;
    178191
     192typedef struct {
     193        amdm37x_gpt_regs_t *regs;
     194        bool special_available;
     195} amdm37x_gpt_t;
     196
     197static inline void amdm37x_gpt_timer_ticks_init(
     198    amdm37x_gpt_t* timer, uintptr_t ioregs, size_t iosize, unsigned hz)
     199{
     200        ASSERT(timer);
     201        /* Map control register */
     202        timer->regs = (void*) km_map(ioregs, iosize, PAGE_NOT_CACHEABLE);
     203
     204        /* Set tldr and tccr */
     205        timer->regs->tldr = 0xffffffff - 32768 / hz;
     206        timer->regs->tccr = 0xffffffff - 32768 / hz;
     207
     208        /* Set autoreload */
     209        timer->regs->tclr = AMDM37x_GPT_TCLR_AR_FLAG;
     210
     211        timer->special_available = (
     212            (ioregs == AMDM37x_GPT1_BASE_ADDRESS) ||
     213            (ioregs == AMDM37x_GPT2_BASE_ADDRESS) ||
     214            (ioregs == AMDM37x_GPT10_BASE_ADDRESS));
     215
     216}
     217
     218static inline void amdm37x_gpt_timer_ticks_start(amdm37x_gpt_t* timer)
     219{
     220        ASSERT(timer);
     221        ASSERT(timer->regs);
     222        /* Enable overflow interrupt */
     223        timer->regs->tier |= AMDM37x_GPT_TIER_OVF_IRQ_FLAG;
     224        /* Start timer */
     225        timer->regs->tclr |= AMDM37x_GPT_TCLR_ST_FLAG;
     226}
     227
    179228#endif
    180229
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