Fork us on GitHub Follow us on Facebook Follow us on Twitter

Changeset a4c066e in mainline


Ignore:
Timestamp:
2017-10-05T10:58:37Z (4 years ago)
Author:
Michal Staruch <salmelu@…>
Branches:
lfn, master
Children:
44063d17
Parents:
0a42d381
Message:

Added TRB macros, qword set

Location:
uspace/drv/bus/usb/xhci/hw_struct
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • uspace/drv/bus/usb/xhci/hw_struct/common.h

    r0a42d381 ra4c066e  
    8181}
    8282
     83static inline void xhci_qword_set_bits(xhci_qword_t *storage, uint64_t value, unsigned hi, unsigned lo)
     84{
     85   const uint64_t mask = host2xhci(64, BIT_RANGE(uint64_t, hi, lo));
     86   const uint64_t set = host2xhci(64, value << lo);
     87   *storage = (*storage & ~mask) | set;
     88}
     89
    8390#endif
    8491
  • uspace/drv/bus/usb/xhci/hw_struct/context.h

    r0a42d381 ra4c066e  
    4949 */
    5050typedef struct xhci_endpoint_ctx {
    51         xhci_dword_t data[5];
     51        xhci_dword_t data[2];
     52        xhci_qword_t data2;
     53        xhci_dword_t data3;
    5254        xhci_dword_t reserved[3];
    5355
     
    6971    xhci_dword_set_bits(&(ctx).data[1], val, 15, 8)
    7072#define XHCI_EP_TR_DPTR_SET(ctx, val) \
    71     xhci_dword_set_bits(&(ctx).data[2], (val >> 4), 63, 4)
     73    xhci_qword_set_bits(&(ctx).data2, (val >> 4), 63, 4)
    7274#define XHCI_EP_DCS_SET(ctx, val) \
    73     xhci_dword_set_bits(&(ctx).data[2], val, 0, 0)
     75    xhci_qword_set_bits(&(ctx).data2, val, 0, 0)
    7476#define XHCI_EP_INTERVAL_SET(ctx, val) \
    7577    xhci_dword_set_bits(&(ctx).data[0], val, 23, 16)
     
    9395#define XHCI_EP_MAX_PACKET_SIZE(ctx)    XHCI_DWORD_EXTRACT((ctx).data[1], 31, 16)
    9496
    95 #define XHCI_EP_DCS(ctx)                XHCI_DWORD_EXTRACT((ctx).data[2],  0,  0)
    96 #define XHCI_EP_TR_DPTR(ctx)            XHCI_DWORD_EXTRACT((ctx).data[2], 63,  4)
     97#define XHCI_EP_DCS(ctx)                XHCI_QWORD_EXTRACT((ctx).data2,  0,  0)
     98#define XHCI_EP_TR_DPTR(ctx)            XHCI_QWORD_EXTRACT((ctx).data2, 63,  4)
    9799
    98100} __attribute__((packed)) xhci_ep_ctx_t;
  • uspace/drv/bus/usb/xhci/hw_struct/trb.h

    r0a42d381 ra4c066e  
    100100#define TRB_CYCLE(trb)          XHCI_DWORD_EXTRACT((trb).control, 0, 0)
    101101#define TRB_LINK_TC(trb)        XHCI_DWORD_EXTRACT((trb).control, 1, 1)
     102
     103#define TRB_CTRL_SET_SETUP_WLENGTH(trb, val) \
     104        xhci_qword_set_bits(&(trb).parameter, val, 63, 48)
     105#define TRB_CTRL_SET_SETUP_WINDEX(trb, val) \
     106        xhci_qword_set_bits(&(trb).parameter, val, 47, 32)
     107#define TRB_CTRL_SET_SETUP_WVALUE(trb, val) \
     108        xhci_qword_set_bits(&(trb).parameter, val, 31, 16)
     109#define TRB_CTRL_SET_SETUP_BREQ(trb, val) \
     110        xhci_qword_set_bits(&(trb).parameter, val, 15, 8)
     111#define TRB_CTRL_SET_SETUP_BMREQTYPE(trb, val) \
     112        xhci_qword_set_bits(&(trb).parameter, val, 7, 0)
     113
     114#define TRB_CTRL_SET_TD_SIZE(trb, val) \
     115        xhci_dword_set_bits(&(trb).status, val, 21, 17)
     116#define TRB_CTRL_SET_XFER_LEN(trb, val) \
     117        xhci_dword_set_bits(&(trb).status, val, 16, 0)
     118
     119#define TRB_CTRL_SET_ENT(trb, val) \
     120        xhci_dword_set_bits(&(trb).control, val, 1, 1)
     121#define TRB_CTRL_SET_ISP(trb, val) \
     122        xhci_dword_set_bits(&(trb).control, val, 2, 2)
     123#define TRB_CTRL_SET_NS(trb, val) \
     124        xhci_dword_set_bits(&(trb).control, val, 3, 3)
     125#define TRB_CTRL_SET_CHAIN(trb, val) \
     126        xhci_dword_set_bits(&(trb).control, val, 4, 4)
     127#define TRB_CTRL_SET_IOC(trb, val) \
     128        xhci_dword_set_bits(&(trb).control, val, 5, 5)
     129#define TRB_CTRL_SET_IDT(trb, val) \
     130        xhci_dword_set_bits(&(trb).control, val, 6, 6)
     131
     132#define TRB_CTRL_SET_TRB_TYPE(trb, val) \
     133        xhci_dword_set_bits(&(trb).control, val, 15, 10)
     134#define TRB_CTRL_SET_DIR(trb, val) \
     135        xhci_dword_set_bits(&(trb).control, val, 16, 16)
     136#define TRB_CTRL_SET_TRT(trb, val) \
     137        xhci_dword_set_bits(&(trb).control, val, 17, 16)
    102138
    103139/**
Note: See TracChangeset for help on using the changeset viewer.