Changes in boot/arch/sparc64/loader/asm.S [e731b0d:a1a83e5e] in mainline
- File:
-
- 1 edited
-
boot/arch/sparc64/loader/asm.S (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
-
boot/arch/sparc64/loader/asm.S
re731b0d ra1a83e5e 31 31 #include <register.h> 32 32 33 .register %g2, #scratch34 .register %g3, #scratch33 .register %g2, #scratch 34 .register %g3, #scratch 35 35 36 36 .text … … 43 43 ba %xcc, halt 44 44 nop 45 46 memcpy: 47 mov %o0, %o3 ! save dst 48 add %o1, 7, %g1 49 and %g1, -8, %g1 50 cmp %o1, %g1 51 be,pn %xcc, 3f 52 add %o0, 7, %g1 53 mov 0, %g3 54 0: 55 brz,pn %o2, 2f 56 mov 0, %g2 57 1: 58 ldub [%g3 + %o1], %g1 59 add %g2, 1, %g2 60 cmp %o2, %g2 61 stb %g1, [%g3 + %o0] 62 bne,pt %xcc, 1b 63 mov %g2, %g3 64 2: 65 jmp %o7 + 8 ! exit point 66 mov %o3, %o0 67 3: 68 and %g1, -8, %g1 69 cmp %o0, %g1 70 bne,pt %xcc, 0b 71 mov 0, %g3 72 srlx %o2, 3, %g4 73 brz,pn %g4, 5f 74 mov 0, %g5 75 4: 76 sllx %g3, 3, %g2 77 add %g5, 1, %g3 78 ldx [%o1 + %g2], %g1 79 mov %g3, %g5 80 cmp %g4, %g3 81 bne,pt %xcc, 4b 82 stx %g1, [%o0 + %g2] 83 5: 84 and %o2, 7, %o2 85 brz,pn %o2, 2b 86 sllx %g4, 3, %g1 87 mov 0, %g2 88 add %g1, %o0, %o0 89 add %g1, %o1, %g4 90 mov 0, %g3 91 6: 92 ldub [%g2 + %g4], %g1 93 stb %g1, [%g2 + %o0] 94 add %g3, 1, %g2 95 cmp %o2, %g2 96 bne,pt %xcc, 6b 97 mov %g2, %g3 45 98 46 memcpy: 47 mov %o0, %o3 ! save dst 48 add %o1, 7, %g1 49 and %g1, -8, %g1 50 cmp %o1, %g1 51 be,pn %xcc, 3f 52 add %o0, 7, %g1 53 mov 0, %g3 54 55 0: 56 brz,pn %o2, 2f 57 mov 0, %g2 58 59 1: 60 ldub [%g3 + %o1], %g1 61 add %g2, 1, %g2 62 cmp %o2, %g2 63 stb %g1, [%g3 + %o0] 64 bne,pt %xcc, 1b 65 mov %g2, %g3 66 67 2: 68 jmp %o7 + 8 ! exit point 69 mov %o3, %o0 70 71 3: 72 and %g1, -8, %g1 73 cmp %o0, %g1 74 bne,pt %xcc, 0b 75 mov 0, %g3 76 srlx %o2, 3, %g4 77 brz,pn %g4, 5f 78 mov 0, %g5 79 80 4: 81 sllx %g3, 3, %g2 82 add %g5, 1, %g3 83 ldx [%o1 + %g2], %g1 84 mov %g3, %g5 85 cmp %g4, %g3 86 bne,pt %xcc, 4b 87 stx %g1, [%o0 + %g2] 88 89 5: 90 and %o2, 7, %o2 91 brz,pn %o2, 2b 92 sllx %g4, 3, %g1 93 mov 0, %g2 94 add %g1, %o0, %o0 95 add %g1, %o1, %g4 96 mov 0, %g3 97 98 6: 99 ldub [%g2 + %g4], %g1 100 stb %g1, [%g2 + %o0] 101 add %g3, 1, %g2 102 cmp %o2, %g2 103 bne,pt %xcc, 6b 104 mov %g2, %g3 105 106 jmp %o7 + 8 ! exit point 107 mov %o3, %o0 99 jmp %o7 + 8 ! exit point 100 mov %o3, %o0 108 101 109 102 jump_to_kernel: … … 114 107 * 3. Flush instruction pipeline. 115 108 */ 116 109 117 110 /* 118 111 * US3 processors have a write-invalidate cache, so explicitly 119 112 * invalidating it is not required. Whether to invalidate I-cache 120 * or not is decided according to the value of the 5th argument121 * (subarchitecture).113 * or not is decided according to the value of the global 114 * "subarchitecture" variable (set in the bootstrap). 122 115 */ 123 cmp %i4, 3 116 set subarchitecture, %g2 117 ldub [%g2], %g2 118 cmp %g2, 3 124 119 be %xcc, 1f 125 120 nop 126 127 0: 128 call icache_flush 129 nop 130 131 1: 132 membar #StoreStore 121 0: 122 call icache_flush 123 nop 124 1: 125 membar #StoreStore 133 126 134 127 /* 135 128 * Flush the instruction pipeline. 136 129 */ 137 flush 138 130 flush %i7 131 139 132 mov %o0, %l1 140 133 mov %o1, %o0 141 134 mov %o2, %o1 142 135 mov %o3, %o2 143 jmp %l1 136 jmp %l1 ! jump to kernel 144 137 nop 145 138 146 #define ICACHE_SIZE 147 #define ICACHE_LINE_SIZE 148 #define ICACHE_SET_BIT 149 #define ASI_ICACHE_TAG 139 #define ICACHE_SIZE 8192 140 #define ICACHE_LINE_SIZE 32 141 #define ICACHE_SET_BIT (1 << 13) 142 #define ASI_ICACHE_TAG 0x67 150 143 151 144 # Flush I-cache 152 145 icache_flush: 153 set ((ICACHE_SIZE - ICACHE_LINE_SIZE) | ICACHE_SET_BIT), %g1 154 stxa %g0, [%g1] ASI_ICACHE_TAG 155 156 0: 157 membar #Sync 158 subcc %g1, ICACHE_LINE_SIZE, %g1 159 bnz,pt %xcc, 0b 160 161 stxa %g0, [%g1] ASI_ICACHE_TAG 162 membar #Sync 146 set ((ICACHE_SIZE - ICACHE_LINE_SIZE) | ICACHE_SET_BIT), %g1 147 stxa %g0, [%g1] ASI_ICACHE_TAG 148 0: membar #Sync 149 subcc %g1, ICACHE_LINE_SIZE, %g1 150 bnz,pt %xcc, 0b 151 stxa %g0, [%g1] ASI_ICACHE_TAG 152 membar #Sync 163 153 retl 164 154 ! SF Erratum #51 165 155 nop 166 167 156 .global ofw 168 157 ofw: … … 170 159 set ofw_cif, %l0 171 160 ldx [%l0], %l0 172 161 173 162 rdpr %pstate, %l1 174 163 and %l1, ~PSTATE_AM_BIT, %l2 175 164 wrpr %l2, 0, %pstate 176 165 177 166 jmpl %l0, %o7 178 167 mov %i0, %o0 179 168 180 169 wrpr %l1, 0, %pstate 181 170 182 171 ret 183 172 restore %o0, 0, %o0
Note:
See TracChangeset
for help on using the changeset viewer.
