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  • uspace/drv/bus/usb/uhci/hc.h

    r7de1988c r9f6cb910  
    3636#define DRV_UHCI_HC_H
    3737
    38 #include <ddf/interrupt.h>
    3938#include <device/hw_res_parsed.h>
    4039#include <fibril.h>
     40#include <macros.h>
     41#include <stdbool.h>
     42#include <sys/types.h>
    4143#include <usb/host/hcd.h>
     44#include <usb/host/usb_transfer_batch.h>
    4245
     46#include "uhci_rh.h"
    4347#include "transfer_list.h"
     48#include "hw_struct/link_pointer.h"
    4449
    4550/** UHCI I/O registers layout */
    4651typedef struct uhci_regs {
    4752        /** Command register, controls HC behaviour */
    48         uint16_t usbcmd;
     53        ioport16_t usbcmd;
    4954#define UHCI_CMD_MAX_PACKET (1 << 7)
    5055#define UHCI_CMD_CONFIGURE  (1 << 6)
     
    5762
    5863        /** Status register, 1 means interrupt is asserted (if enabled) */
    59         uint16_t usbsts;
     64        ioport16_t usbsts;
    6065#define UHCI_STATUS_HALTED (1 << 5)
    6166#define UHCI_STATUS_PROCESS_ERROR (1 << 4)
     
    6873
    6974        /** Interrupt enabled registers */
    70         uint16_t usbintr;
     75        ioport16_t usbintr;
    7176#define UHCI_INTR_SHORT_PACKET (1 << 3)
    7277#define UHCI_INTR_COMPLETE (1 << 2)
     
    7580
    7681        /** Register stores frame number used in SOF packet */
    77         uint16_t frnum;
     82        ioport16_t frnum;
    7883
    7984        /** Pointer(physical) to the Frame List */
    80         uint32_t flbaseadd;
     85        ioport32_t flbaseadd;
    8186
    8287        /** SOF modification to match external timers */
    83         uint8_t sofmod;
     88        ioport8_t sofmod;
     89
     90        PADD8[3];
     91        ioport16_t ports[];
    8492} uhci_regs_t;
    8593
    8694#define UHCI_FRAME_LIST_COUNT 1024
    87 #define UHCI_INT_EMULATOR_TIMEOUT 10000
    8895#define UHCI_DEBUGER_TIMEOUT 5000000
    8996#define UHCI_ALLOWED_HW_FAIL 5
    90 #define UHCI_NEEDED_IRQ_COMMANDS 5
    9197
    9298/** Main UHCI driver structure */
    9399typedef struct hc {
    94         /** Generic HCD driver structure */
    95         hcd_t generic;
    96 
     100        uhci_rh_t rh;
    97101        /** Addresses of I/O registers */
    98102        uhci_regs_t *registers;
     
    112116        /** Pointer table to the above lists, helps during scheduling */
    113117        transfer_list_t *transfers[2][4];
    114         /** Fibril periodically checking status register*/
    115         fid_t interrupt_emulator;
    116118        /** Indicator of hw interrupts availability */
    117119        bool hw_interrupts;
     
    121123} hc_t;
    122124
    123 int hc_register_irq_handler(ddf_dev_t *, addr_range_t *, int,
    124     interrupt_handler_t);
    125 int hc_get_irq_code(irq_pio_range_t [], size_t, irq_cmd_t [], size_t,
    126     addr_range_t *);
    127 void hc_interrupt(hc_t *instance, uint16_t status);
    128 int hc_init(hc_t *instance, addr_range_t *regs, bool interupts);
     125int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res, bool interupts);
     126void hc_fini(hc_t *instance);
    129127
    130 /** Safely dispose host controller internal structures
    131  *
    132  * @param[in] instance Host controller structure to use.
    133  */
    134 static inline void hc_fini(hc_t *instance) {} /* TODO: implement*/
     128int uhci_hc_gen_irq_code(irq_code_t *code, const hw_res_list_parsed_t *hw_res);
     129
     130void uhci_hc_interrupt(hcd_t *hcd, uint32_t status);
     131int uhci_hc_status(hcd_t *hcd, uint32_t *status);
     132int uhci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch);
     133
    135134#endif
    136135
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