Changes in kernel/arch/arm32/src/mm/page_fault.c [ecd1a0a:9d58539] in mainline

File:

• kernel/arch/arm32/src/mm/page_fault.c (modified) (6 diffs)

kernel/arch/arm32/src/mm/page_fault.c

@@ -42 +42 @@
 #include <print.h>
 
-/** Returns value stored in comnbined/data fault status register.
+/** Returns value stored in fault status register.
  *
  *  @return Value stored in CP15 fault status register (FSR).
- *
- *  "VMSAv6 added a fifth fault status bit (bit[10]) to both the IFSR and DFSR.
- *  It is IMPLEMENTATION DEFINED how this bit is encoded in earlier versions of
- *  the architecture. A write flag (bit[11] of the DFSR) has also been
- *  introduced."
- *  ARM Architecture Reference Manual version i ch. B4.6 (PDF p. 719)
- *
- *  See ch. B4.9.6 for location of data/instruction FSR.
- *
- */
-static inline fault_status_t read_data_fault_status_register(void)
-{
-        fault_status_t fsu;
-        
-        /* Combined/Data fault status is stored in CP15 register 5, c0. */
+ */
+static inline fault_status_t read_fault_status_register(void)
+{
+        fault_status_union_t fsu;
+        
+        /* fault status is stored in CP15 register 5 */
         asm volatile (
                 "mrc p15, 0, %[dummy], c5, c0, 0"
-                : [dummy] "=r" (fsu.raw)
+                : [dummy] "=r" (fsu.dummy)
         );
         
-        return fsu;
-}
-
-/** Returns DFAR (fault address register) content.
- *
- * This register is equivalent to FAR on pre armv6 machines.
- *
- * @return DFAR (fault address register) content (address that caused a page
+        return fsu.fs;
+}
+
+/** Returns FAR (fault address register) content.
+ *
+ * @return FAR (fault address register) content (address that caused a page
  *         fault)
  */
-static inline uintptr_t read_data_fault_address_register(void)
+static inline uintptr_t read_fault_address_register(void)
 {
         uintptr_t ret;
@@ -133 +122 @@
 }
 
-#if defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
 /** Decides whether read or write into memory is requested.
  *
@@ -154 +142 @@
                 panic("page_fault - instruction does not access memory "
                     "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
-                    *(uint32_t*)instr_union.instr, (void *) badvaddr);
+                    instr_union.pc, (void *) badvaddr);
                 return PF_ACCESS_EXEC;
         }
@@ -174 +162 @@
         panic("page_fault - instruction doesn't access memory "
             "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
-            *(uint32_t*)instr_union.instr, (void *) badvaddr);
+            instr_union.pc, (void *) badvaddr);
 
         return PF_ACCESS_EXEC;
 }
-#endif
 
 /** Handles "data abort" exception (load or store at invalid address).
@@ -188 +175 @@
 void data_abort(unsigned int exc_no, istate_t *istate)
 {
-        uintptr_t badvaddr = read_data_fault_address_register();
-
-#if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a)
-        fault_status_t fsr = read_data_fault_status_register();
-        const pf_access_t access =
-            fsr.data.wr ? PF_ACCESS_WRITE : PF_ACCESS_READ;
-#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
-        const pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
-#else
-#error "Unsupported architecture"
-#endif
+        fault_status_t fsr __attribute__ ((unused)) =
+            read_fault_status_register();
+        uintptr_t badvaddr = read_fault_address_register();
+
+        pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
+
         int ret = as_page_fault(badvaddr, access, istate);
 
@@ -215 +197 @@
 void prefetch_abort(unsigned int exc_no, istate_t *istate)
 {
-        /* NOTE: We should use IFAR and IFSR here. */
         int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);