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  • boot/arch/arm32/src/mm.c

    r2e55443 r9d58539  
    3838#include <arch/mm.h>
    3939
    40 /** Disable the MMU */
    41 static void disable_paging(void)
    42 {
    43         asm volatile (
    44                 "mrc p15, 0, r0, c1, c0, 0\n"
    45                 "bic r0, r0, #1\n"
    46                 "mcr p15, 0, r0, c1, c0, 0\n"
    47                 ::: "r0"
    48         );
    49 }
    50 
    51 /** Check if caching can be enabled for a given memory section.
    52  *
    53  * Memory areas used for I/O are excluded from caching.
    54  * At the moment caching is enabled only on GTA02.
    55  *
    56  * @param section       The section number.
    57  *
    58  * @return      1 if the given section can be mapped as cacheable, 0 otherwise.
    59 */
    60 static inline int section_cacheable(pfn_t section)
    61 {
    62 #ifdef MACHINE_gta02
    63         unsigned long address = section << PTE_SECTION_SHIFT;
    64 
    65         if (address >= GTA02_IOMEM_START && address < GTA02_IOMEM_END)
    66                 return 0;
    67         else
    68                 return 1;
    69 #elif defined MACHINE_beagleboardxm
    70         const unsigned long address = section << PTE_SECTION_SHIFT;
    71         if (address >= BBXM_RAM_START && address < BBXM_RAM_END)
    72                 return 1;
    73 #elif defined MACHINE_beaglebone
    74         const unsigned long address = section << PTE_SECTION_SHIFT;
    75         if (address >= AM335x_RAM_START && address < AM335x_RAM_END)
    76                 return 1;
    77 #endif
    78         return 0;
    79 }
    80 
    8140/** Initialize "section" page table entry.
    8241 *
    … …  
    9554{
    9655        pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
    97         pte->bufferable = 1;
    98         pte->cacheable = section_cacheable(frame);
    99         pte->xn = 0;
     56        pte->bufferable = 0;
     57        pte->cacheable = 0;
     58        pte->impl_specific = 0;
    10059        pte->domain = 0;
    10160        pte->should_be_zero_1 = 0;
    102         pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW;
    103         pte->tex = 0;
    104         pte->access_permission_1 = 0;
    105         pte->shareable = 0;
    106         pte->non_global = 0;
     61        pte->access_permission = PTE_AP_USER_NO_KERNEL_RW;
    10762        pte->should_be_zero_2 = 0;
    108         pte->non_secure = 0;
    10963        pte->section_base_addr = frame;
    11064}
    … …  
    11367static void init_boot_pt(void)
    11468{
    115         const pfn_t split_page = PTL0_ENTRIES;
     69        pfn_t split_page = 0x800;
     70       
    11671        /* Create 1:1 virtual-physical mapping (in lower 2 GB). */
    11772        pfn_t page;
    11873        for (page = 0; page < split_page; page++)
    11974                init_ptl0_section(&boot_pt[page], page);
     75       
     76        /*
     77         * Create 1:1 virtual-physical mapping in kernel space
     78         * (upper 2 GB), physical addresses start from 0.
     79         */
     80        for (page = split_page; page < PTL0_ENTRIES; page++)
     81                init_ptl0_section(&boot_pt[page], page - split_page);
    12082       
    12183        asm volatile (
    … …  
    13395                /* Behave as a client of domains */
    13496                "ldr r0, =0x55555555\n"
    135                 "mcr p15, 0, r0, c3, c0, 0\n"
    136 
     97                "mcr p15, 0, r0, c3, c0, 0\n" 
     98               
    13799                /* Current settings */
    138100                "mrc p15, 0, r0, c1, c0, 0\n"
    139101               
    140                 /* Enable ICache, DCache, BPredictors and MMU,
    141                  * we disable caches before jumping to kernel
    142                  * so this is safe for all archs.
    143                  */
    144                 "ldr r1, =0x00001805\n"
     102                /* Mask to enable paging */
     103                "ldr r1, =0x00000001\n"
     104                "orr r0, r0, r1\n"
    145105               
    146                 "orr r0, r0, r1\n"
    147 
    148                 /* Invalidate the TLB content before turning on the MMU.
    149                  * ARMv7-A Reference manual, B3.10.3
    150                  */
    151                 "mcr p15, 0, r0, c8, c7, 0\n"
    152                
    153                 /* Store settings, enable the MMU */
     106                /* Store settings */
    154107                "mcr p15, 0, r0, c1, c0, 0\n"
    155108                ::: "r0", "r1"
    … …  
    159112/** Start the MMU - initialize page table and enable paging. */
    160113void mmu_start() {
    161         disable_paging();
    162114        init_boot_pt();
    163115        enable_paging();
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