Changes in kernel/arch/ia32/include/asm.h [3d6beaa:96b02eb9] in mainline
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kernel/arch/ia32/include/asm.h
r3d6beaa r96b02eb9 41 41 #include <typedefs.h> 42 42 #include <config.h> 43 44 extern uint32_t interrupt_handler_size; 45 46 extern void paging_on(void); 47 48 extern void interrupt_handlers(void); 49 50 extern void enable_l_apic_in_msr(void); 51 52 53 extern void asm_delay_loop(uint32_t t); 54 extern void asm_fake_loop(uint32_t t); 55 43 #include <trace.h> 56 44 57 45 /** Halt CPU … … 60 48 * 61 49 */ 62 static inline __attribute__((noreturn)) void cpu_halt(void)50 NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void) 63 51 { 64 52 while (true) { … … 69 57 } 70 58 71 static inline void cpu_sleep(void) 72 { 73 asm volatile ("hlt\n"); 74 } 75 76 #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ 59 NO_TRACE static inline void cpu_sleep(void) 60 { 61 asm volatile ( 62 "hlt\n" 63 ); 64 } 65 66 #define GEN_READ_REG(reg) NO_TRACE static inline sysarg_t read_ ##reg (void) \ 77 67 { \ 78 unative_t res; \68 sysarg_t res; \ 79 69 asm volatile ( \ 80 70 "movl %%" #reg ", %[res]" \ … … 84 74 } 85 75 86 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \76 #define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (sysarg_t regn) \ 87 77 { \ 88 78 asm volatile ( \ … … 119 109 * 120 110 */ 121 static inline void pio_write_8(ioport8_t *port, uint8_t val)111 NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val) 122 112 { 123 113 asm volatile ( 124 114 "outb %b[val], %w[port]\n" 125 :: [val] "a" (val), [port] "d" (port) 115 :: [val] "a" (val), 116 [port] "d" (port) 126 117 ); 127 118 } … … 135 126 * 136 127 */ 137 static inline void pio_write_16(ioport16_t *port, uint16_t val)128 NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val) 138 129 { 139 130 asm volatile ( 140 131 "outw %w[val], %w[port]\n" 141 :: [val] "a" (val), [port] "d" (port) 132 :: [val] "a" (val), 133 [port] "d" (port) 142 134 ); 143 135 } … … 151 143 * 152 144 */ 153 static inline void pio_write_32(ioport32_t *port, uint32_t val)145 NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val) 154 146 { 155 147 asm volatile ( 156 148 "outl %[val], %w[port]\n" 157 :: [val] "a" (val), [port] "d" (port) 149 :: [val] "a" (val), 150 [port] "d" (port) 158 151 ); 159 152 } … … 167 160 * 168 161 */ 169 static inline uint8_t pio_read_8(ioport8_t *port)162 NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) 170 163 { 171 164 uint8_t val; … … 188 181 * 189 182 */ 190 static inline uint16_t pio_read_16(ioport16_t *port)183 NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) 191 184 { 192 185 uint16_t val; … … 209 202 * 210 203 */ 211 static inline uint32_t pio_read_32(ioport32_t *port)204 NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) 212 205 { 213 206 uint32_t val; … … 230 223 * 231 224 */ 232 static inline ipl_t interrupts_enable(void)225 NO_TRACE static inline ipl_t interrupts_enable(void) 233 226 { 234 227 ipl_t v; … … 252 245 * 253 246 */ 254 static inline ipl_t interrupts_disable(void)247 NO_TRACE static inline ipl_t interrupts_disable(void) 255 248 { 256 249 ipl_t v; … … 273 266 * 274 267 */ 275 static inline void interrupts_restore(ipl_t ipl)268 NO_TRACE static inline void interrupts_restore(ipl_t ipl) 276 269 { 277 270 asm volatile ( … … 287 280 * 288 281 */ 289 static inline ipl_t interrupts_read(void)282 NO_TRACE static inline ipl_t interrupts_read(void) 290 283 { 291 284 ipl_t v; … … 305 298 * 306 299 */ 307 static inline bool interrupts_disabled(void)300 NO_TRACE static inline bool interrupts_disabled(void) 308 301 { 309 302 ipl_t v; … … 319 312 320 313 /** Write to MSR */ 321 static inline void write_msr(uint32_t msr, uint64_t value)314 NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value) 322 315 { 323 316 asm volatile ( 324 317 "wrmsr" 325 :: "c" (msr), "a" ((uint32_t) (value)), 318 :: "c" (msr), 319 "a" ((uint32_t) (value)), 326 320 "d" ((uint32_t) (value >> 32)) 327 321 ); 328 322 } 329 323 330 static inline uint64_t read_msr(uint32_t msr)324 NO_TRACE static inline uint64_t read_msr(uint32_t msr) 331 325 { 332 326 uint32_t ax, dx; … … 334 328 asm volatile ( 335 329 "rdmsr" 336 : "=a" (ax), "=d" (dx) 330 : "=a" (ax), 331 "=d" (dx) 337 332 : "c" (msr) 338 333 ); … … 349 344 * 350 345 */ 351 static inline uintptr_t get_stack_base(void)346 NO_TRACE static inline uintptr_t get_stack_base(void) 352 347 { 353 348 uintptr_t v; … … 367 362 * 368 363 */ 369 static inline void invlpg(uintptr_t addr)364 NO_TRACE static inline void invlpg(uintptr_t addr) 370 365 { 371 366 asm volatile ( 372 367 "invlpg %[addr]\n" 373 :: [addr] "m" (*( unative_t *) addr)368 :: [addr] "m" (*(sysarg_t *) addr) 374 369 ); 375 370 } … … 380 375 * 381 376 */ 382 static inline void gdtr_load(ptr_16_32_t *gdtr_reg)377 NO_TRACE static inline void gdtr_load(ptr_16_32_t *gdtr_reg) 383 378 { 384 379 asm volatile ( … … 393 388 * 394 389 */ 395 static inline void gdtr_store(ptr_16_32_t *gdtr_reg)390 NO_TRACE static inline void gdtr_store(ptr_16_32_t *gdtr_reg) 396 391 { 397 392 asm volatile ( … … 406 401 * 407 402 */ 408 static inline void idtr_load(ptr_16_32_t *idtr_reg)403 NO_TRACE static inline void idtr_load(ptr_16_32_t *idtr_reg) 409 404 { 410 405 asm volatile ( … … 419 414 * 420 415 */ 421 static inline void tr_load(uint16_t sel)416 NO_TRACE static inline void tr_load(uint16_t sel) 422 417 { 423 418 asm volatile ( … … 427 422 } 428 423 424 extern void paging_on(void); 425 extern void enable_l_apic_in_msr(void); 426 427 extern void asm_delay_loop(uint32_t); 428 extern void asm_fake_loop(uint32_t); 429 430 extern uintptr_t int_syscall; 431 432 extern uintptr_t int_0; 433 extern uintptr_t int_1; 434 extern uintptr_t int_2; 435 extern uintptr_t int_3; 436 extern uintptr_t int_4; 437 extern uintptr_t int_5; 438 extern uintptr_t int_6; 439 extern uintptr_t int_7; 440 extern uintptr_t int_8; 441 extern uintptr_t int_9; 442 extern uintptr_t int_10; 443 extern uintptr_t int_11; 444 extern uintptr_t int_12; 445 extern uintptr_t int_13; 446 extern uintptr_t int_14; 447 extern uintptr_t int_15; 448 extern uintptr_t int_16; 449 extern uintptr_t int_17; 450 extern uintptr_t int_18; 451 extern uintptr_t int_19; 452 extern uintptr_t int_20; 453 extern uintptr_t int_21; 454 extern uintptr_t int_22; 455 extern uintptr_t int_23; 456 extern uintptr_t int_24; 457 extern uintptr_t int_25; 458 extern uintptr_t int_26; 459 extern uintptr_t int_27; 460 extern uintptr_t int_28; 461 extern uintptr_t int_29; 462 extern uintptr_t int_30; 463 extern uintptr_t int_31; 464 extern uintptr_t int_32; 465 extern uintptr_t int_33; 466 extern uintptr_t int_34; 467 extern uintptr_t int_35; 468 extern uintptr_t int_36; 469 extern uintptr_t int_37; 470 extern uintptr_t int_38; 471 extern uintptr_t int_39; 472 extern uintptr_t int_40; 473 extern uintptr_t int_41; 474 extern uintptr_t int_42; 475 extern uintptr_t int_43; 476 extern uintptr_t int_44; 477 extern uintptr_t int_45; 478 extern uintptr_t int_46; 479 extern uintptr_t int_47; 480 extern uintptr_t int_48; 481 extern uintptr_t int_49; 482 extern uintptr_t int_50; 483 extern uintptr_t int_51; 484 extern uintptr_t int_52; 485 extern uintptr_t int_53; 486 extern uintptr_t int_54; 487 extern uintptr_t int_55; 488 extern uintptr_t int_56; 489 extern uintptr_t int_57; 490 extern uintptr_t int_58; 491 extern uintptr_t int_59; 492 extern uintptr_t int_60; 493 extern uintptr_t int_61; 494 extern uintptr_t int_62; 495 extern uintptr_t int_63; 496 429 497 #endif 430 498
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