Changeset 946b630 in mainline


Ignore:
Timestamp:
2005-09-03T21:01:23Z (19 years ago)
Author:
Ondrej Palkovsky <ondrap@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
5260478
Parents:
c835e7c
Message:

Reverted APIC mapping back to identity mapping.
Added AMD64 SMP support. Works now!

Location:
arch
Files:
1 added
7 edited

Legend:

Unmodified
Added
Removed
  • arch/amd64/Makefile.inc

    rc835e7c r946b630  
    5353
    5454ifdef SMP
    55 arch_sources += arch/smp/apic.c \
     55arch_sources += arch/smp/ap.S \
     56                arch/smp/apic.c \
    5657                arch/smp/ipi.c \
    5758                arch/smp/mps.c \
  • arch/amd64/_link.ld

    rc835e7c r946b630  
    5656                kdata_end = .;
    5757        }
    58         _map_address = 0xffffffff80100000;
     58        _boot_offset = 0x100000;
     59        _ka2pa_offset = 0xffffffff80000000;
     60        _map_address = _ka2pa_offset + _boot_offset;
     61
    5962        _hardcoded_kernel_size = (ktext_end - ktext_start) + (unmapped_ktext_end - unmapped_ktext_start) + (kdata_end - kdata_start) + (unmapped_kdata_end - unmapped_kdata_start);
    6063
    6164        e820table_boot = e820table - _map_address;
    6265        e820counter_boot = e820counter - _map_address;
     66        ap_bootstrap_gdtr = ap_bootstrap_gdtr_boot + _ka2pa_offset;
    6367}
  • arch/amd64/src/boot/boot.S

    rc835e7c r946b630  
    8383        jmp 1b
    8484
    85 # Protected 16-bit. We want to reuse the code-seg descriptor,
    86 # the Default operand size must not be 1 when entering long mode       
     85# Protected 32-bit. We want to reuse the code-seg descriptor,
     86# the Default operand size must not be 1 when entering long mode
     87.code32
    8788now_in_prot: 
    8889        # Set up stack & data descriptors
    8990        movw $gdtselector(KDATA_DES), %ax
    9091        movw %ax, %ds
    91         movw %ax, %fs
    92         movw %ax, %gs
    9392        movw %ax, %ss
    9493
     
    172171        .word gdtselector(GDT_ITEMS)
    173172        .long KA2PA(gdt)-BOOT_OFFSET
    174 
    175 .global ap_bootstrap_gdtr
    176 ap_bootstrap_gdtr:
    177         .word gdtselector(GDT_ITEMS)
    178         .long KA2PA(gdt)-BOOT_OFFSET
  • arch/amd64/src/dummy.s

    rc835e7c r946b630  
    2828
    2929.text
    30 
    31 .global ap_boot
    32        
    33 ap_boot:       
    34         ret
  • arch/amd64/src/pm.c

    rc835e7c r946b630  
    9292          .granularity = 1,
    9393          .base_24_31  = 0 },
    94         /* KTEXT 16-bit protected */
     94        /* KTEXT 32-bit protected */
    9595        { .limit_0_15  = 0xffff,
    9696          .base_0_15   = 0,
     
    100100          .available   = 0,
    101101          .longmode    = 0,
    102           .special     = 0,
     102          .special     = 1,
    103103          .granularity = 1,
    104104          .base_24_31  = 0 },
  • arch/ia32/src/smp/mps.c

    rc835e7c r946b630  
    224224        }
    225225       
    226         l_apic = (__u32 *)PA2KA((__address)ct->l_apic);
     226        l_apic = (__u32 *)(__address)ct->l_apic;
    227227
    228228        cnt = 0;
     
    334334        }
    335335       
    336         io_apic = (__u32 *)PA2KA((__address)ioa->io_apic);
     336        io_apic = (__u32 *)(__address)ioa->io_apic;
    337337}
    338338
  • arch/ia32/src/smp/smp.c

    rc835e7c r946b630  
    6262        }
    6363
    64         if (config.cpu_count > 1) {
    65                 map_page_to_frame((__address)l_apic, KA2PA((__address)l_apic),
     64        if (config.cpu_count > 1) {             
     65                map_page_to_frame((__address)l_apic, (__address)l_apic,
    6666                                  PAGE_NOT_CACHEABLE, 0);
    67                 map_page_to_frame((__address) io_apic, 
    68                                   KA2PA((__address) io_apic),
     67                map_page_to_frame((__address) io_apic,
     68                                  (__address) io_apic,
    6969                                  PAGE_NOT_CACHEABLE, 0);
    7070        }
Note: See TracChangeset for help on using the changeset viewer.