Changeset 87e5b526 in mainline


Ignore:
Timestamp:
2012-09-04T21:28:19Z (12 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
23c1fae
Parents:
1ef7fb2
Message:

arm32: Drop the old instruction recognition.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/src/mm/page_fault.c

    r1ef7fb2 r87e5b526  
    7777}
    7878
    79 /** Decides whether the instruction is load/store or not.
    80  *
    81  * @param instr Instruction
    82  *
    83  * @return true when instruction is load/store, false otherwise
    84  *
    85  */
    86 static inline bool is_load_store_instruction(instruction_t instr)
    87 {
    88         /* load store immediate offset */
    89         if (instr.type == 0x2)
    90                 return true;
    91        
    92         /* load store register offset */
    93         if ((instr.type == 0x3) && (instr.bit4 == 0))
    94                 return true;
    95        
    96         /* load store multiple */
    97         if (instr.type == 0x4)
    98                 return true;
    99        
    100         /* oprocessor load/store */
    101         if (instr.type == 0x6)
    102                 return true;
    103        
    104         return false;
    105 }
    106 
    107 /** Decides whether the instruction is swap or not.
    108  *
    109  * @param instr Instruction
    110  *
    111  * @return true when instruction is swap, false otherwise
    112  */
    113 static inline bool is_swap_instruction(instruction_t instr)
    114 {
    115         /* swap, swapb instruction */
    116         if ((instr.type == 0x0) &&
    117             ((instr.opcode == 0x8) || (instr.opcode == 0xa)) &&
    118             (instr.access == 0x0) && (instr.bits567 == 0x4) && (instr.bit4 == 1))
    119                 return true;
    120        
    121         return false;
    122 }
    123 
    12479/** Decides whether read or write into memory is requested.
    12580 *
     
    170125                { 0x0fb00000, 0x01000000, PF_ACCESS_WRITE },
    171126        };
    172         pf_access_t access = PF_ACCESS_UNKNOWN;
    173127        uint32_t inst = *(uint32_t*)instr_addr;
    174128        for (unsigned i = 0; i < sizeof(ls_inst) / sizeof(ls_inst[0]); ++i) {
    175129                if ((inst & ls_inst[i].mask) == ls_inst[i].value) {
    176                         if (access != PF_ACCESS_UNKNOWN)
    177                                 printf("Double match: %x %u\n", inst, i);
    178                         access = ls_inst[i].access;
     130                        return ls_inst[i].access;
    179131                }
    180         }
    181 
    182         /* load store instructions */
    183         if (is_load_store_instruction(instr)) {
    184                 if (instr.access == 1) {
    185                         if (access != PF_ACCESS_READ)
    186                                 printf("MISMATCH READ(%u): %x\n", access, inst);
    187                         return PF_ACCESS_READ;
    188                 } else {
    189                         if (access != PF_ACCESS_WRITE)
    190                                 printf("MISMATCH WRITE(%u): %x\n", access, inst);
    191                         return PF_ACCESS_WRITE;
    192                 }
    193         }
    194 
    195         /* swap, swpb instruction */
    196         if (is_swap_instruction(instr)) {
    197                 if (access != PF_ACCESS_WRITE)
    198                         printf("MISMATCH WRITE(%u): %x\n", access, inst);
    199                 return PF_ACCESS_WRITE;
    200132        }
    201133
     
    203135            "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
    204136            instr_union.pc, (void *) badvaddr);
    205 
    206         return PF_ACCESS_EXEC;
    207137}
    208138
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