Changeset 86b31ba9 in mainline

Timestamp:

2006-09-26T16:12:38Z (18 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a9ac978

Parents:

26678e5

Message:

Implement spinlock and test_and_set for sparc64.

Location:

kernel/arch/sparc64/include

Files:

• atomic.h (modified) (2 diffs)
• barrier.h (modified) (1 diff)

kernel/arch/sparc64/include/atomic.h

@@ -36 +36 @@
 #define KERN_sparc64_ATOMIC_H_
 
+#include <arch/barrier.h>
 #include <arch/types.h>
 #include <typedefs.h>
@@ -93 +94 @@
 }
 
+static inline long test_and_set(atomic_t *val)
+{
+        uint64_t v = 1;
+
+        __asm__ volatile ("casx %0, %2, %1\n" : "+m" (*val), "+r" (v) : "r" (0));
+
+        return v;
+}
+
+static inline void atomic_lock_arch(atomic_t *val)
+{
+        uint64_t tmp1 = 1;
+        uint64_t tmp2;
+
+        __asm__ volatile (
+        "0:\n"
+                "casx %0, %3, %1\n"
+                "brz %1, 2f\n"
+                "nop\n"
+        "1:\n"
+                "ldx %0, %2\n"
+                "brz %2, 0b\n"
+                "nop\n"
+                "ba 1b\n"
+                "nop\n"
+        "2:\n"
+                : "+m" (*val), "+r" (tmp1), "+r" (tmp2) : "r" (0)
+        );
+        
+        /*
+         * Prevent critical section code from bleeding out this way up.
+         */
+        CS_ENTER_BARRIER();
+}
+
 #endif
 

kernel/arch/sparc64/include/barrier.h

@@ -37 +37 @@
 
 /*
- * TODO: Implement true SPARC V9 memory barriers for macros below.
+ * We assume TSO memory model in which only reads can pass earlier stores
+ * (but not earlier reads). Therefore, CS_ENTER_BARRIER() and CS_LEAVE_BARRIER()
+ * can be empty.
  */
 #define CS_ENTER_BARRIER()      __asm__ volatile ("" ::: "memory")