Changeset 802bb95 in mainline

Timestamp:

2005-11-09T22:31:34Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

13fe013

Parents:

2ccd275

Message:

ia64 work.
Comment some offending steps of heavyweight interrupt handler regarding RSE switching.
With this change, ia64 will do well on tests rwlock #4 and thread #1.
Cleanup.

Location:

arch/ia64/src

Files:

• cpu/cpu.c (modified) (1 diff)
• ivt.S (modified) (4 diffs)
• start.S (modified) (2 diffs)

arch/ia64/src/cpu/cpu.c

@@ +1 @@
+/*
+ * Copyright (C) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
 #include <cpu.h>
-#include <print.h>
-#include <panic.h>
-#include <arch/types.h>
 
 void cpu_arch_init(void)
 {
-        int psr = 0x2000;
-    
-        __asm__  volatile (
-                "{mov psr.l = %0 ;;}\n"
-                "{srlz.i;"
-                "srlz.d ;;}"
-                : 
-                : "r" (psr)
-        );
-
-        /* Switch to register bank 1. */
-        __asm__ volatile 
-        (
-            "bsw.1;;\n"
-        );             
-        
 }
 

arch/ia64/src/ivt.S

@@ -107 +107 @@
         
         /* assume kernel backing store */
-        mov ar.bspstore = r28 ;;
+        /* mov ar.bspstore = r28 ;; */
         
         mov r29 = ar.bsp
@@ -147 +147 @@
         ld8 r24 = [r31], +8 ;;          /* load ar.rsc */
 
-        mov ar.bspstore = r28 ;;        /* (step 4) */
-        mov ar.rnat = r27               /* (step 5) */
+        /* mov ar.bspstore = r28 ;; */  /* (step 4) */
+        /* mov ar.rnat = r27 */         /* (step 5) */
 
         mov ar.pfs = r25                /* (step 6) */
@@ -248 +248 @@
     
     /* 9. skipped (will not enable interrupts) */
+        /*
+         * ssm PSR_I_MASK
+         * ;;
+         * srlz.d
+         */
 
     /* 10. call handler */
@@ -257 +262 @@
         
     /* 12. skipped (will not disable interrupts) */
+        /*
+         * rsm PSR_I_MASK
+         * ;;
+         * srlz.d
+         */
 
     /* 13. restore general and floating-point registers */

arch/ia64/src/start.S

@@ -27 +27 @@
 #
 
+#include <arch/register.h>
+
 .section K_TEXT_START
 
@@ -39 +41 @@
         srlz.i
         srlz.d
+        ssm PSR_IC_MASK
+        srlz.d
+        
+        # switch to register bank 1
+        bsw.1
         
         # initialize register stack