Changes in uspace/drv/bus/usb/uhci/hc.h [9f6cb910:7de1988c] in mainline
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uspace/drv/bus/usb/uhci/hc.h
r9f6cb910 r7de1988c 36 36 #define DRV_UHCI_HC_H 37 37 38 #include <ddf/interrupt.h> 38 39 #include <device/hw_res_parsed.h> 39 40 #include <fibril.h> 40 #include <macros.h>41 #include <stdbool.h>42 #include <sys/types.h>43 41 #include <usb/host/hcd.h> 44 #include <usb/host/usb_transfer_batch.h>45 42 46 #include "uhci_rh.h"47 43 #include "transfer_list.h" 48 #include "hw_struct/link_pointer.h"49 44 50 45 /** UHCI I/O registers layout */ 51 46 typedef struct uhci_regs { 52 47 /** Command register, controls HC behaviour */ 53 ioport16_t usbcmd;48 uint16_t usbcmd; 54 49 #define UHCI_CMD_MAX_PACKET (1 << 7) 55 50 #define UHCI_CMD_CONFIGURE (1 << 6) … … 62 57 63 58 /** Status register, 1 means interrupt is asserted (if enabled) */ 64 ioport16_t usbsts;59 uint16_t usbsts; 65 60 #define UHCI_STATUS_HALTED (1 << 5) 66 61 #define UHCI_STATUS_PROCESS_ERROR (1 << 4) … … 73 68 74 69 /** Interrupt enabled registers */ 75 ioport16_t usbintr;70 uint16_t usbintr; 76 71 #define UHCI_INTR_SHORT_PACKET (1 << 3) 77 72 #define UHCI_INTR_COMPLETE (1 << 2) … … 80 75 81 76 /** Register stores frame number used in SOF packet */ 82 ioport16_t frnum;77 uint16_t frnum; 83 78 84 79 /** Pointer(physical) to the Frame List */ 85 ioport32_t flbaseadd;80 uint32_t flbaseadd; 86 81 87 82 /** SOF modification to match external timers */ 88 ioport8_t sofmod; 89 90 PADD8[3]; 91 ioport16_t ports[]; 83 uint8_t sofmod; 92 84 } uhci_regs_t; 93 85 94 86 #define UHCI_FRAME_LIST_COUNT 1024 87 #define UHCI_INT_EMULATOR_TIMEOUT 10000 95 88 #define UHCI_DEBUGER_TIMEOUT 5000000 96 89 #define UHCI_ALLOWED_HW_FAIL 5 90 #define UHCI_NEEDED_IRQ_COMMANDS 5 97 91 98 92 /** Main UHCI driver structure */ 99 93 typedef struct hc { 100 uhci_rh_t rh; 94 /** Generic HCD driver structure */ 95 hcd_t generic; 96 101 97 /** Addresses of I/O registers */ 102 98 uhci_regs_t *registers; … … 116 112 /** Pointer table to the above lists, helps during scheduling */ 117 113 transfer_list_t *transfers[2][4]; 114 /** Fibril periodically checking status register*/ 115 fid_t interrupt_emulator; 118 116 /** Indicator of hw interrupts availability */ 119 117 bool hw_interrupts; … … 123 121 } hc_t; 124 122 125 int hc_init(hc_t *instance, const hw_res_list_parsed_t *hw_res, bool interupts); 126 void hc_fini(hc_t *instance); 123 int hc_register_irq_handler(ddf_dev_t *, addr_range_t *, int, 124 interrupt_handler_t); 125 int hc_get_irq_code(irq_pio_range_t [], size_t, irq_cmd_t [], size_t, 126 addr_range_t *); 127 void hc_interrupt(hc_t *instance, uint16_t status); 128 int hc_init(hc_t *instance, addr_range_t *regs, bool interupts); 127 129 128 int uhci_hc_gen_irq_code(irq_code_t *code, const hw_res_list_parsed_t *hw_res); 129 130 void uhci_hc_interrupt(hcd_t *hcd, uint32_t status); 131 int uhci_hc_status(hcd_t *hcd, uint32_t *status); 132 int uhci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch); 133 130 /** Safely dispose host controller internal structures 131 * 132 * @param[in] instance Host controller structure to use. 133 */ 134 static inline void hc_fini(hc_t *instance) {} /* TODO: implement*/ 134 135 #endif 135 136
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