Changeset 7dc8bf1 in mainline


Ignore:
Timestamp:
2013-01-10T22:33:02Z (12 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
97718a5
Parents:
1f271d9
Message:

arm32: Implement barriers for armv7-a

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/include/barrier.h

    r1f271d9 r7dc8bf1  
    4949#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
    5050
     51#if defined PROCESSOR_ARCH_armv7_a
     52/* ARMv7 uses instructions for memory barriers see ARM Architecture reference
     53 * manual for details:
     54 * DMB: ch. A8.8.43 page A8-376
     55 * DSB: ch. A8.8.44 page A8-378
     56 * See ch. A3.8.3 page A3-148 for details about memory barrier implementation
     57 * and functionality on armv7 architecture.
     58 */
     59#define memory_barrier()  asm volatile ("dmb" ::: "memory")
     60#define read_barrier()    asm volatile ("dsb" ::: "memory")
     61#define write_barrier()   asm volatile ("dsb st" ::: "memory")
     62#else
    5163#define memory_barrier()  asm volatile ("" ::: "memory")
    5264#define read_barrier()    asm volatile ("" ::: "memory")
    5365#define write_barrier()   asm volatile ("" ::: "memory")
    54 
     66#endif
    5567/*
    5668 * There are multiple ways ICache can be implemented on ARM machines. Namely
     
    6880 */
    6981
    70 /* Available on both all supported arms,
     82#ifdef PROCESSOR_ARCH_armv7_a
     83#define smc_coherence(a) asm volatile ( "isb" ::: "memory")
     84#define smc_coherence_block(a, l) smc_coherence(a)
     85#else
     86/* Available on all supported arms,
    7187 * invalidates entire ICache so the written value does not matter. */
     88//TODO might be PL1 only on armv5 -
    7289#define smc_coherence(a) asm volatile ( "mcr p15, 0, r0, c7, c5, 0")
    7390#define smc_coherence_block(a, l) smc_coherence(a)
     91#endif
    7492
    7593
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