Changes in kernel/arch/ppc32/include/barrier.h [d92bf462:7b187ef] in mainline

File:

• kernel/arch/ppc32/include/barrier.h (modified) (3 diffs)

kernel/arch/ppc32/include/barrier.h

@@ -27 +27 @@
  */
 
-/** @addtogroup ppc32
+/** @addtogroup ppc32   
  * @{
  */
@@ -36 +36 @@
 #define KERN_ppc32_BARRIER_H_
 
-#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
-#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
+#define CS_ENTER_BARRIER()      asm volatile ("" ::: "memory")
+#define CS_LEAVE_BARRIER()      asm volatile ("" ::: "memory")
 
-#define memory_barrier()  asm volatile ("sync" ::: "memory")
-#define read_barrier()    asm volatile ("sync" ::: "memory")
-#define write_barrier()   asm volatile ("eieio" ::: "memory")
-
-#define instruction_barrier() \
-        asm volatile ( \
-                "sync\n" \
-                "isync\n" \
-        )
-
-#define COHERENCE_INVAL_MIN  4
+#define memory_barrier() asm volatile ("sync" ::: "memory")
+#define read_barrier() asm volatile ("sync" ::: "memory")
+#define write_barrier() asm volatile ("eieio" ::: "memory")
 
 /*
@@ -61 +53 @@
 {
         asm volatile (
-                "dcbst 0, %[addr]\n"
+                "dcbst 0, %0\n"
                 "sync\n"
-                "icbi 0, %[addr]\n"
+                "icbi 0, %0\n"
                 "sync\n"
                 "isync\n"
-                :: [addr] "r" (addr)
+                :: "r" (addr)
         );
 }
 
-static inline void smc_coherence_block(void *addr, unsigned int len)
+#define COHERENCE_INVAL_MIN     4
+
+static inline void smc_coherence_block(void *addr, unsigned long len)
 {
-        unsigned int i;
-        
-        for (i = 0; i < len; i += COHERENCE_INVAL_MIN)
-                asm volatile (
-                        "dcbst 0, %[addr]\n"
-                        :: [addr] "r" (addr + i)
-                );
-        
-        memory_barrier();
-        
-        for (i = 0; i < len; i += COHERENCE_INVAL_MIN)
-                asm volatile (
-                        "icbi 0, %[addr]\n"
-                        :: [addr] "r" (addr + i)
-                );
-        
-        instruction_barrier();
+        unsigned long i;
+
+        for (i = 0; i < len; i += COHERENCE_INVAL_MIN) {
+                asm volatile ("dcbst 0, %0\n" :: "r" (addr + i));
+        }
+
+        asm volatile ("sync");
+
+        for (i = 0; i < len; i += COHERENCE_INVAL_MIN) {
+                asm volatile ("icbi 0, %0\n" :: "r" (addr + i));
+        }
+
+        asm volatile (
+                "sync\n"
+                "isync\n"
+        );
 }