Changes in uspace/srv/hw/netif/dp8390/dp8390.h [3c106e88:7922dea] in mainline
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uspace/srv/hw/netif/dp8390/dp8390.h (modified) (3 diffs)
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uspace/srv/hw/netif/dp8390/dp8390.h
r3c106e88 r7922dea 38 38 */ 39 39 40 /** @addtogroup ne200040 /** @addtogroup dp8390 41 41 * @{ 42 42 */ … … 49 49 #define __NET_NETIF_DP8390_H__ 50 50 51 #include <fibril_synch.h>52 51 #include <net/packet.h> 53 54 /** Module name */ 55 #define NAME "ne2000" 52 #include "dp8390_port.h" 56 53 57 54 /** Input/output size */ 58 #define NE2K_IO_SIZE 0x0020 59 60 /** Ethernet address length */ 61 #define ETH_ADDR 6 55 #define DP8390_IO_SIZE 0x0020 62 56 63 57 /* National Semiconductor DP8390 Network Interface Controller. */ … … 111 105 #define DP_MAR7 0x0f /**< Multicast Address Register 7 */ 112 106 113 /* Bits in Command Register */ 114 #define CR_STP 0x01 /**< Stop (software reset) */ 115 #define CR_STA 0x02 /**< Start (activate NIC) */ 116 #define CR_TXP 0x04 /**< Transmit Packet */ 117 #define CR_DMA 0x38 /**< Mask for DMA control */ 118 #define CR_DM_NOP 0x00 /**< DMA: No Operation */ 119 #define CR_DM_RR 0x08 /**< DMA: Remote Read */ 120 #define CR_DM_RW 0x10 /**< DMA: Remote Write */ 121 #define CR_DM_SP 0x18 /**< DMA: Send Packet */ 122 #define CR_DM_ABORT 0x20 /**< DMA: Abort Remote DMA Operation */ 123 #define CR_PS 0xc0 /**< Mask for Page Select */ 124 #define CR_PS_P0 0x00 /**< Register Page 0 */ 125 #define CR_PS_P1 0x40 /**< Register Page 1 */ 126 #define CR_PS_P2 0x80 /**< Register Page 2 */ 127 #define CR_PS_T1 0xc0 /**< Test Mode Register Map */ 128 129 /* Bits in Interrupt State Register */ 130 #define ISR_PRX 0x01 /**< Packet Received with no errors */ 131 #define ISR_PTX 0x02 /**< Packet Transmitted with no errors */ 132 #define ISR_RXE 0x04 /**< Receive Error */ 133 #define ISR_TXE 0x08 /**< Transmit Error */ 134 #define ISR_OVW 0x10 /**< Overwrite Warning */ 135 #define ISR_CNT 0x20 /**< Counter Overflow */ 136 #define ISR_RDC 0x40 /**< Remote DMA Complete */ 137 #define ISR_RST 0x80 /**< Reset Status */ 138 139 /* Bits in Interrupt Mask Register */ 140 #define IMR_PRXE 0x01 /**< Packet Received Interrupt Enable */ 141 #define IMR_PTXE 0x02 /**< Packet Transmitted Interrupt Enable */ 142 #define IMR_RXEE 0x04 /**< Receive Error Interrupt Enable */ 143 #define IMR_TXEE 0x08 /**< Transmit Error Interrupt Enable */ 144 #define IMR_OVWE 0x10 /**< Overwrite Warning Interrupt Enable */ 145 #define IMR_CNTE 0x20 /**< Counter Overflow Interrupt Enable */ 146 #define IMR_RDCE 0x40 /**< DMA Complete Interrupt Enable */ 147 148 /* Bits in Data Configuration Register */ 149 #define DCR_WTS 0x01 /**< Word Transfer Select */ 150 #define DCR_BYTEWIDE 0x00 /**< WTS: byte wide transfers */ 151 #define DCR_WORDWIDE 0x01 /**< WTS: word wide transfers */ 152 #define DCR_BOS 0x02 /**< Byte Order Select */ 153 #define DCR_LTLENDIAN 0x00 /**< BOS: Little Endian */ 154 #define DCR_BIGENDIAN 0x02 /**< BOS: Big Endian */ 155 #define DCR_LAS 0x04 /**< Long Address Select */ 156 #define DCR_BMS 0x08 /**< Burst Mode Select */ 157 #define DCR_AR 0x10 /**< Autoinitialize Remote */ 158 #define DCR_FTS 0x60 /**< Fifo Threshold Select */ 159 #define DCR_2BYTES 0x00 /**< 2 bytes */ 160 #define DCR_4BYTES 0x40 /**< 4 bytes */ 161 #define DCR_8BYTES 0x20 /**< 8 bytes */ 162 #define DCR_12BYTES 0x60 /**< 12 bytes */ 163 164 /* Bits in Transmit Configuration Register */ 165 #define TCR_CRC 0x01 /**< Inhibit CRC */ 166 #define TCR_ELC 0x06 /**< Encoded Loopback Control */ 167 #define TCR_NORMAL 0x00 /**< ELC: Normal Operation */ 168 #define TCR_INTERNAL 0x02 /**< ELC: Internal Loopback */ 169 #define TCR_0EXTERNAL 0x04 /**< ELC: External Loopback LPBK=0 */ 170 #define TCR_1EXTERNAL 0x06 /**< ELC: External Loopback LPBK=1 */ 171 #define TCR_ATD 0x08 /**< Auto Transmit Disable */ 172 #define TCR_OFST 0x10 /**< Collision Offset Enable (be nice) */ 173 174 /* Bits in Interrupt Status Register */ 175 #define TSR_PTX 0x01 /**< Packet Transmitted (without error) */ 176 #define TSR_DFR 0x02 /**< Transmit Deferred (reserved) */ 177 #define TSR_COL 0x04 /**< Transmit Collided */ 178 #define TSR_ABT 0x08 /**< Transmit Aborted */ 179 #define TSR_CRS 0x10 /**< Carrier Sense Lost */ 180 #define TSR_FU 0x20 /**< FIFO Underrun */ 181 #define TSR_CDH 0x40 /**< CD Heartbeat */ 182 #define TSR_OWC 0x80 /**< Out of Window Collision */ 183 184 /* Bits in Receive Configuration Register */ 185 #define RCR_SEP 0x01 /**< Save Errored Packets */ 186 #define RCR_AR 0x02 /**< Accept Runt Packets */ 187 #define RCR_AB 0x04 /**< Accept Broadcast */ 188 #define RCR_AM 0x08 /**< Accept Multicast */ 189 #define RCR_PRO 0x10 /**< Physical Promiscuous */ 190 #define RCR_MON 0x20 /**< Monitor Mode */ 191 192 /* Bits in Receive Status Register */ 193 #define RSR_PRX 0x01 /**< Packet Received Intact */ 194 #define RSR_CRC 0x02 /**< CRC Error */ 195 #define RSR_FAE 0x04 /**< Frame Alignment Error */ 196 #define RSR_FO 0x08 /**< FIFO Overrun */ 197 #define RSR_MPA 0x10 /**< Missed Packet */ 198 #define RSR_PHY 0x20 /**< Multicast Address Match */ 199 #define RSR_DIS 0x40 /**< Receiver Disabled */ 200 #define RSR_DFR 0x80 /**< In later manuals: Deferring */ 201 202 typedef struct { 203 /* Device configuration */ 204 void *port; 205 void *data_port; 206 int irq; 207 uint8_t mac[ETH_ADDR]; 208 209 uint8_t start_page; /**< Ring buffer start page */ 210 uint8_t stop_page; /**< Ring buffer stop page */ 211 212 /* Send queue */ 213 struct { 214 bool dirty; /**< Buffer contains a packet */ 215 size_t size; /**< Packet size */ 216 uint8_t page; /**< Starting page of the buffer */ 217 } sq; 218 fibril_mutex_t sq_mutex; 219 fibril_condvar_t sq_cv; 220 221 /* Driver run-time variables */ 222 bool probed; 107 /* Bits in dp_cr */ 108 #define CR_STP 0x01 /* Stop: software reset */ 109 #define CR_STA 0x02 /* Start: activate NIC */ 110 #define CR_TXP 0x04 /* Transmit Packet */ 111 #define CR_DMA 0x38 /* Mask for DMA control */ 112 #define CR_DM_NOP 0x00 /* DMA: No Operation */ 113 #define CR_DM_RR 0x08 /* DMA: Remote Read */ 114 #define CR_DM_RW 0x10 /* DMA: Remote Write */ 115 #define CR_DM_SP 0x18 /* DMA: Send Packet */ 116 #define CR_DM_ABORT 0x20 /* DMA: Abort Remote DMA Operation */ 117 #define CR_PS 0xC0 /* Mask for Page Select */ 118 #define CR_PS_P0 0x00 /* Register Page 0 */ 119 #define CR_PS_P1 0x40 /* Register Page 1 */ 120 #define CR_PS_P2 0x80 /* Register Page 2 */ 121 #define CR_PS_T1 0xC0 /* Test Mode Register Map */ 122 123 /* Bits in dp_isr */ 124 #define ISR_PRX 0x01 /* Packet Received with no errors */ 125 #define ISR_PTX 0x02 /* Packet Transmitted with no errors */ 126 #define ISR_RXE 0x04 /* Receive Error */ 127 #define ISR_TXE 0x08 /* Transmit Error */ 128 #define ISR_OVW 0x10 /* Overwrite Warning */ 129 #define ISR_CNT 0x20 /* Counter Overflow */ 130 #define ISR_RDC 0x40 /* Remote DMA Complete */ 131 #define ISR_RST 0x80 /* Reset Status */ 132 133 /* Bits in dp_imr */ 134 #define IMR_PRXE 0x01 /* Packet Received iEnable */ 135 #define IMR_PTXE 0x02 /* Packet Transmitted iEnable */ 136 #define IMR_RXEE 0x04 /* Receive Error iEnable */ 137 #define IMR_TXEE 0x08 /* Transmit Error iEnable */ 138 #define IMR_OVWE 0x10 /* Overwrite Warning iEnable */ 139 #define IMR_CNTE 0x20 /* Counter Overflow iEnable */ 140 #define IMR_RDCE 0x40 /* DMA Complete iEnable */ 141 142 /* Bits in dp_dcr */ 143 #define DCR_WTS 0x01 /* Word Transfer Select */ 144 #define DCR_BYTEWIDE 0x00 /* WTS: byte wide transfers */ 145 #define DCR_WORDWIDE 0x01 /* WTS: word wide transfers */ 146 #define DCR_BOS 0x02 /* Byte Order Select */ 147 #define DCR_LTLENDIAN 0x00 /* BOS: Little Endian */ 148 #define DCR_BIGENDIAN 0x02 /* BOS: Big Endian */ 149 #define DCR_LAS 0x04 /* Long Address Select */ 150 #define DCR_BMS 0x08 /* Burst Mode Select 151 * Called Loopback Select (LS) in 152 * later manuals. Should be set. */ 153 #define DCR_AR 0x10 /* Autoinitialize Remote */ 154 #define DCR_FTS 0x60 /* Fifo Threshold Select */ 155 #define DCR_2BYTES 0x00 /* 2 bytes */ 156 #define DCR_4BYTES 0x40 /* 4 bytes */ 157 #define DCR_8BYTES 0x20 /* 8 bytes */ 158 #define DCR_12BYTES 0x60 /* 12 bytes */ 159 160 /* Bits in dp_tcr */ 161 #define TCR_CRC 0x01 /* Inhibit CRC */ 162 #define TCR_ELC 0x06 /* Encoded Loopback Control */ 163 #define TCR_NORMAL 0x00 /* ELC: Normal Operation */ 164 #define TCR_INTERNAL 0x02 /* ELC: Internal Loopback */ 165 #define TCR_0EXTERNAL 0x04 /* ELC: External Loopback LPBK=0 */ 166 #define TCR_1EXTERNAL 0x06 /* ELC: External Loopback LPBK=1 */ 167 #define TCR_ATD 0x08 /* Auto Transmit Disable */ 168 #define TCR_OFST 0x10 /* Collision Offset Enable (be nice) */ 169 170 /* Bits in dp_tsr */ 171 #define TSR_PTX 0x01 /* Packet Transmitted (without error)*/ 172 #define TSR_DFR 0x02 /* Transmit Deferred, reserved in 173 * later manuals. */ 174 #define TSR_COL 0x04 /* Transmit Collided */ 175 #define TSR_ABT 0x08 /* Transmit Aborted */ 176 #define TSR_CRS 0x10 /* Carrier Sense Lost */ 177 #define TSR_FU 0x20 /* FIFO Underrun */ 178 #define TSR_CDH 0x40 /* CD Heartbeat */ 179 #define TSR_OWC 0x80 /* Out of Window Collision */ 180 181 /* Bits in tp_rcr */ 182 #define RCR_SEP 0x01 /* Save Errored Packets */ 183 #define RCR_AR 0x02 /* Accept Runt Packets */ 184 #define RCR_AB 0x04 /* Accept Broadcast */ 185 #define RCR_AM 0x08 /* Accept Multicast */ 186 #define RCR_PRO 0x10 /* Physical Promiscuous */ 187 #define RCR_MON 0x20 /* Monitor Mode */ 188 189 /* Bits in dp_rsr */ 190 #define RSR_PRX 0x01 /* Packet Received Intact */ 191 #define RSR_CRC 0x02 /* CRC Error */ 192 #define RSR_FAE 0x04 /* Frame Alignment Error */ 193 #define RSR_FO 0x08 /* FIFO Overrun */ 194 #define RSR_MPA 0x10 /* Missed Packet */ 195 #define RSR_PHY 0x20 /* Multicast Address Match */ 196 #define RSR_DIS 0x40 /* Receiver Disabled */ 197 #define RSR_DFR 0x80 /* In later manuals: Deferring */ 198 199 /** Type definition of the receive header 200 * 201 */ 202 typedef struct dp_rcvhdr { 203 /** Copy of rsr */ 204 uint8_t dr_status; 205 206 /** Pointer to next packet */ 207 uint8_t dr_next; 208 209 /** Receive Byte Count Low */ 210 uint8_t dr_rbcl; 211 212 /** Receive Byte Count High */ 213 uint8_t dr_rbch; 214 } dp_rcvhdr_t; 215 216 /** Page size */ 217 #define DP_PAGESIZE 256 218 219 /** Read 1 byte from the zero page register. 220 * @param[in] dep The network interface structure. 221 * @param[in] reg The register offset. 222 * @returns The read value. 223 */ 224 #define inb_reg0(dep, reg) (inb(dep->de_dp8390_port + reg)) 225 226 /** Write 1 byte zero page register. 227 * @param[in] dep The network interface structure. 228 * @param[in] reg The register offset. 229 * @param[in] data The value to be written. 230 */ 231 #define outb_reg0(dep, reg, data) (outb(dep->de_dp8390_port + reg, data)) 232 233 /** Read 1 byte from the first page register. 234 * @param[in] dep The network interface structure. 235 * @param[in] reg The register offset. 236 * @returns The read value. 237 */ 238 #define inb_reg1(dep, reg) (inb(dep->de_dp8390_port + reg)) 239 240 /** Write 1 byte first page register. 241 * @param[in] dep The network interface structure. 242 * @param[in] reg The register offset. 243 * @param[in] data The value to be written. 244 */ 245 #define outb_reg1(dep, reg, data) (outb(dep->de_dp8390_port + reg, data)) 246 247 #define SENDQ_NR 2 /* Maximum size of the send queue */ 248 #define SENDQ_PAGES 6 /* 6 * DP_PAGESIZE >= 1514 bytes */ 249 250 typedef struct dpeth { 251 /* 252 * The de_base_port field is the starting point of the probe. 253 * The conf routine also fills de_irq. If the probe 254 * routine knows the irq and/or memory address because they are 255 * hardwired in the board, the probe should modify these fields. 256 */ 257 port_t de_base_port; 258 int de_irq; 259 260 ether_addr_t de_address; 261 port_t de_dp8390_port; 262 port_t de_data_port; 263 int de_16bit; 264 long de_ramsize; 265 int de_offset_page; 266 int de_startpage; 267 int de_stoppage; 268 269 /* Do it yourself send queue */ 270 struct sendq { 271 int sq_filled; /* this buffer contains a packet */ 272 int sq_size; /* with this size */ 273 int sq_sendpage; /* starting page of the buffer */ 274 } de_sendq[SENDQ_NR]; 275 276 int de_sendq_nr; 277 int de_sendq_head; /* Enqueue at the head */ 278 int de_sendq_tail; /* Dequeue at the tail */ 279 280 /* Fields for internal use by the dp8390 driver. */ 281 eth_stat_t de_stat; 282 283 /* Driver flags */ 223 284 bool up; 224 225 /* Device statistics */ 226 device_stats_t stats; 227 uint64_t misses; /**< Receive frame misses */ 228 uint64_t underruns; /**< FIFO underruns */ 229 uint64_t overruns; /**< FIFO overruns */ 230 } ne2k_t; 231 232 extern int ne2k_probe(ne2k_t *, void *, int); 233 extern int ne2k_up(ne2k_t *); 234 extern void ne2k_down(ne2k_t *); 235 extern void ne2k_send(ne2k_t *, packet_t *); 236 extern void ne2k_interrupt(ne2k_t *, uint8_t isr, int, device_id_t); 285 bool enabled; 286 bool stopped; 287 bool sending; 288 bool send_avail; 289 } dpeth_t; 237 290 238 291 #endif
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