Changes in kernel/arch/sparc64/src/mm/sun4v/tsb.c [8c2214e:74cbac7d] in mainline
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kernel/arch/sparc64/src/mm/sun4v/tsb.c
r8c2214e r74cbac7d 1 1 /* 2 2 * Copyright (c) 2006 Jakub Jermar 3 * Copyright (c) 2009 Pavel Rimsky4 3 * All rights reserved. 5 4 * … … 35 34 36 35 #include <arch/mm/tsb.h> 37 #include <arch/mm/pagesize.h>38 36 #include <arch/mm/tlb.h> 39 37 #include <arch/mm/page.h> … … 51 49 * portions of both TSBs are invalidated at a time. 52 50 * 53 * @param as 54 * @param page 55 * @param pages Number of pages to invalidate. Value of ( count_t) -1 means the56 * 51 * @param as Address space. 52 * @param page First page to invalidate in TSB. 53 * @param pages Number of pages to invalidate. Value of (size_t) -1 means the 54 * whole TSB. 57 55 */ 58 56 void tsb_invalidate(as_t *as, uintptr_t page, size_t pages) 59 57 { 60 size_t i0, i; 58 size_t i0; 59 size_t i; 61 60 size_t cnt; 62 61 63 ASSERT(as->arch. tsb_description.tsb_base);62 ASSERT(as->arch.itsb && as->arch.dtsb); 64 63 65 64 i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK; 66 ASSERT(i0 < TSB_ENTRY_COUNT);65 ASSERT(i0 < ITSB_ENTRY_COUNT && i0 < DTSB_ENTRY_COUNT); 67 66 68 if (pages == (size_t) - 1 || (pages) >TSB_ENTRY_COUNT)69 cnt = TSB_ENTRY_COUNT;67 if (pages == (size_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT) 68 cnt = ITSB_ENTRY_COUNT; 70 69 else 71 cnt = pages ;70 cnt = pages * 2; 72 71 73 72 for (i = 0; i < cnt; i++) { 74 ((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[ 75 (i0 + i) & (TSB_ENTRY_COUNT - 1)].data.v = false; 73 as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid = 74 true; 75 as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid = 76 true; 76 77 } 77 78 } … … 80 81 * 81 82 * @param t Software PTE. 83 * @param index Zero if lower 8K-subpage, one if higher 8K subpage. 82 84 */ 83 void itsb_pte_copy(pte_t *t )85 void itsb_pte_copy(pte_t *t, size_t index) 84 86 { 87 #if 0 85 88 as_t *as; 86 89 tsb_entry_t *tsb; 87 90 size_t entry; 88 91 92 ASSERT(index <= 1); 93 89 94 as = t->as; 90 entry = ( t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;91 ASSERT(entry < TSB_ENTRY_COUNT);92 tsb = & ((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[entry];95 entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; 96 ASSERT(entry < ITSB_ENTRY_COUNT); 97 tsb = &as->arch.itsb[entry]; 93 98 94 99 /* … … 98 103 */ 99 104 100 tsb->data.v = false; 105 tsb->tag.invalid = true; /* invalidate the entry 106 * (tag target has this 107 * set to 0) */ 101 108 102 109 write_barrier(); 103 110 111 tsb->tag.context = as->asid; 112 /* the shift is bigger than PAGE_WIDTH, do not bother with index */ 104 113 tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; 105 106 114 tsb->data.value = 0; 107 tsb->data.nfo = false; 108 tsb->data.ra = t->frame >> MMU_FRAME_WIDTH; 109 tsb->data.ie = false; 110 tsb->data.e = false; 115 tsb->data.size = PAGESIZE_8K; 116 tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index; 111 117 tsb->data.cp = t->c; /* cp as cache in phys.-idxed, c as cacheable */ 112 tsb->data.cv = false;113 118 tsb->data.p = t->k; /* p as privileged, k as kernel */ 114 tsb->data.x = true; 115 tsb->data.w = false; 116 tsb->data.size = PAGESIZE_8K; 119 tsb->data.v = t->p; /* v as valid, p as present */ 117 120 118 121 write_barrier(); 119 122 120 tsb->data.v = t->p; /* v as valid, p as present */ 123 tsb->tag.invalid = false; /* mark the entry as valid */ 124 #endif 121 125 } 122 126 … … 124 128 * 125 129 * @param t Software PTE. 130 * @param index Zero if lower 8K-subpage, one if higher 8K-subpage. 126 131 * @param ro If true, the mapping is copied read-only. 127 132 */ 128 void dtsb_pte_copy(pte_t *t, bool ro)133 void dtsb_pte_copy(pte_t *t, size_t index, bool ro) 129 134 { 135 #if 0 130 136 as_t *as; 131 137 tsb_entry_t *tsb; 132 138 size_t entry; 139 140 ASSERT(index <= 1); 133 141 134 142 as = t->as; 135 entry = ( t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;136 ASSERT(entry < TSB_ENTRY_COUNT);137 tsb = & ((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[entry];143 entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; 144 ASSERT(entry < DTSB_ENTRY_COUNT); 145 tsb = &as->arch.dtsb[entry]; 138 146 139 147 /* … … 143 151 */ 144 152 145 tsb->data.v = false; 153 tsb->tag.invalid = true; /* invalidate the entry 154 * (tag target has this 155 * set to 0) */ 146 156 147 157 write_barrier(); 148 158 159 tsb->tag.context = as->asid; 160 /* the shift is bigger than PAGE_WIDTH, do not bother with index */ 149 161 tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; 150 151 162 tsb->data.value = 0; 152 tsb->data.nfo = false; 153 tsb->data.ra = t->frame >> MMU_FRAME_WIDTH; 154 tsb->data.ie = false; 155 tsb->data.e = false; 156 tsb->data.cp = t->c; /* cp as cache in phys.-idxed, c as cacheable */ 163 tsb->data.size = PAGESIZE_8K; 164 tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index; 165 tsb->data.cp = t->c; 157 166 #ifdef CONFIG_VIRT_IDX_DCACHE 158 167 tsb->data.cv = t->c; 159 168 #endif /* CONFIG_VIRT_IDX_DCACHE */ 160 tsb->data.p = t->k; /* p as privileged, k as kernel */ 161 tsb->data.x = true; 169 tsb->data.p = t->k; /* p as privileged */ 162 170 tsb->data.w = ro ? false : t->w; 163 tsb->data. size = PAGESIZE_8K;171 tsb->data.v = t->p; 164 172 165 173 write_barrier(); 166 174 167 tsb->data.v = t->p; /* v as valid, p as present */ 175 tsb->tag.invalid = false; /* mark the entry as valid */ 176 #endif 168 177 } 169 178 170 179 /** @} 171 180 */ 181
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