Changes in kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h [cade9c1:730ff63] in mainline

File:

• kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h (modified) (4 diffs)

kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h

@@ -73 +73 @@
 
 .macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
-        mov TT_FAST_INSTRUCTION_ACCESS_MMU_MISS, %g2
-        clr %g5         ! XXX
-        PREEMPTIBLE_HANDLER exc_dispatch 
+        PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
 .endm
 
@@ -125 +123 @@
          * mapped. In such a case, this handler will be called from TL = 1.
          * We handle the situation by pretending that the MMU miss occurred
-         * on TL = 0. Once the MMU miss trap is serviced, the instruction which
+         * on TL = 0. Once the MMU miss trap is services, the instruction which
          * caused the spill/fill trap is restarted, the spill/fill trap occurs,
-         * but this time its handler accesses memory which is mapped.
+         * but this time its handler accesse memory which IS mapped.
          */
         .if (\tl > 0)
@@ -133 +131 @@
         .endif
 
-        mov TT_FAST_DATA_ACCESS_MMU_MISS, %g2
+        /*
+         * Save the faulting virtual page and faulting context to the %g2
+         * register. The most significant 51 bits of the %g2 register will
+         * contain the virtual address which caused the fault truncated to the
+         * page boundary. The least significant 13 bits of the %g2 register
+         * will contain the number of the context in which the fault occurred.
+         * The value of the %g2 register will be passed as a parameter to the
+         * higher level service routine.
+         */
+        or %g1, %g3, %g2
 
-        /*
-         * Save the faulting virtual page and faulting context to the %g5
-         * register. The most significant 51 bits of the %g5 register will
-         * contain the virtual address which caused the fault truncated to the
-         * page boundary. The least significant 13 bits of the %g5 register
-         * will contain the number of the context in which the fault occurred.
-         * The value of the %g5 register will be stored in the istate structure
-         * for inspeciton by the higher level service routine.
-         */
-        or %g1, %g3, %g5
-
-        PREEMPTIBLE_HANDLER exc_dispatch
+        PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
 .endm
 
@@ -174 +170 @@
         sllx %g1, TTE_DATA_TADDR_OFFSET, %g1
 
-        mov TT_FAST_DATA_ACCESS_PROTECTION, %g2
+        /* the same as for FAST_DATA_ACCESS_MMU_MISS_HANDLER */
+        or %g1, %g3, %g2
 
-        /* the same as for FAST_DATA_ACCESS_MMU_MISS_HANDLER */
-        or %g1, %g3, %g5
-
-        PREEMPTIBLE_HANDLER exc_dispatch 
+        PREEMPTIBLE_HANDLER fast_data_access_protection
 .endm
 #endif /* __ASM__ */