Changes in kernel/arch/mips32/include/arch/mm/page.h [85147f3:6ecf5b8] in mainline

File:

• kernel/arch/mips32/include/arch/mm/page.h (modified) (3 diffs)

kernel/arch/mips32/include/arch/mm/page.h

@@ -27 +27 @@
  */
 
-/** @addtogroup mips32mm
+/** @addtogroup mips32mm        
  * @{
  */
@@ -70 +70 @@
  * - PTL3 has 4096 entries (12 bits)
  */
-
+ 
 /* Macros describing number of entries in each level. */
-#define PTL0_ENTRIES_ARCH  64
-#define PTL1_ENTRIES_ARCH  0
-#define PTL2_ENTRIES_ARCH  0
-#define PTL3_ENTRIES_ARCH  4096
+#define PTL0_ENTRIES_ARCH       64
+#define PTL1_ENTRIES_ARCH       0
+#define PTL2_ENTRIES_ARCH       0
+#define PTL3_ENTRIES_ARCH       4096
 
 /* Macros describing size of page tables in each level. */
-#define PTL0_FRAMES_ARCH  1
-#define PTL1_FRAMES_ARCH  1
-#define PTL2_FRAMES_ARCH  1
-#define PTL3_FRAMES_ARCH  1
+#define PTL0_SIZE_ARCH          ONE_FRAME
+#define PTL1_SIZE_ARCH          0
+#define PTL2_SIZE_ARCH          0
+#define PTL3_SIZE_ARCH          ONE_FRAME
 
 /* Macros calculating entry indices for each level. */
-#define PTL0_INDEX_ARCH(vaddr)  ((vaddr) >> 26)
-#define PTL1_INDEX_ARCH(vaddr)  0
-#define PTL2_INDEX_ARCH(vaddr)  0
-#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 14) & 0xfff)
+#define PTL0_INDEX_ARCH(vaddr)  ((vaddr) >> 26) 
+#define PTL1_INDEX_ARCH(vaddr)  0
+#define PTL2_INDEX_ARCH(vaddr)  0
+#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 14) & 0xfff)
 
 /* Set accessor for PTL0 address. */
 #define SET_PTL0_ADDRESS_ARCH(ptl0)
 
-/* Get PTE address accessors for each level. */
+/* Get PTE address accessors for each level. */ 
 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
         (((pte_t *) (ptl0))[(i)].pfn << 12)
@@ -196 +196 @@
         p->p = 1;
 }
+        
 
 extern void page_arch_init(void);