Changeset 69bd642 in mainline


Ignore:
Timestamp:
2005-09-01T15:47:50Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
3c56c94
Parents:
79c1593
Message:

Fix addresses in GDT and IDT to be virtual addresses.

Location:
arch/ia32/src
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • arch/ia32/src/boot/boot.S

    r79c1593 r69bd642  
    5151       
    5252        lgdt gdtr                       # initialize Global Descriptor Table register
    53         lidt idtr                       # initialize Interrupt Descriptor Table register
    5453       
    5554        movl %cr0,%eax
     
    7473       
    7574        lgdt gdtr
    76         lidt idtr
    7775
    7876meeting_point:
  • arch/ia32/src/pm.c

    r79c1593 r69bd642  
    166166        struct descriptor *gdt_p = (struct descriptor *) PA2KA(gdtr.base);
    167167
     168
     169        /*
     170         * Update addresses in GDT and IDT to their virtual counterparts.
     171         */
     172        gdtr.base = KA2PA(gdtr.base);
     173        idtr.base = (__address) idt;
     174        __asm__ volatile ("lgdt %0\n" : : "m" (gdtr));
     175        __asm__ volatile ("lidt %0\n" : : "m" (idtr)); 
     176       
    168177        /*
    169178         * Each CPU has its private GDT and TSS.
     
    198207         * to its own TSS. We just need to load the TR register.
    199208         */
    200         __asm__("ltr %0" : : "r" ((__u16) selector(TSS_DES)));
     209        __asm__ volatile ("ltr %0" : : "r" ((__u16) selector(TSS_DES)));
    201210       
    202211        clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels */
  • arch/ia32/src/smp/ap.S

    r79c1593 r69bd642  
    5252
    5353        lgdt gdtr                       # initialize Global Descriptor Table register
    54         lidt idtr                       # initialize Interrupt Descriptor Table register
    5554       
    5655        movl %cr0,%eax
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